[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)

[Matt Arsenault via llvm-commits]

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@@ -348,6 +351,116 @@ bool AMDGPURegBankCombinerImpl::matchFPMed3ToClamp(MachineInstr &MI,
   return false;
 }
 
+bool AMDGPURegBankCombinerImpl::matchPromote16to32(MachineInstr &MI) const {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  const auto *RB = MRI.getRegBankOrNull(Dst);
+
+  // Only promote uniform instructions.
+  if (RB->getID() != AMDGPU::SGPRRegBankID)
+    return false;
+
+  // Promote only if:
+  //    - We have 16 bit insts (not true 16 bit insts).
----------------
arsenm wrote:

> I guess if you do not have 16-bit VALU instructions then these 16-bit ops would already have been legalized to 32-bit

Yes, but that should already be obvious from what types are legal at this point 

https://github.com/llvm/llvm-project/pull/106557