[llvm] [llvm] Ensure that soft float targets don't emit `fma()` libcalls. (PR #106615)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 15 05:08:19 PDT 2024
================
@@ -0,0 +1,225 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=s390x --fp-contract off < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-OFF
+; RUN: llc -mtriple=s390x --fp-contract on < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-ON
+; RUN: llc -mtriple=s390x --fp-contract fast < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-FAST
+
+define float @fmuladd_intrinsic_f32(float %a, float %b, float %c) #0 {
+; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_intrinsic_f32:
+; SOFT-FLOAT-FPC-OFF: # %bb.0:
+; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-OFF-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_intrinsic_f32:
+; SOFT-FLOAT-FPC-ON: # %bb.0:
+; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-ON-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_intrinsic_f32:
+; SOFT-FLOAT-FPC-FAST: # %bb.0:
+; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-FAST-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
+ %result = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
+ ret float %result
+}
+
+define double @fmuladd_intrinsic_f64(double %a, double %b, double %c) #0 {
+; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_intrinsic_f64:
+; SOFT-FLOAT-FPC-OFF: # %bb.0:
+; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_intrinsic_f64:
+; SOFT-FLOAT-FPC-ON: # %bb.0:
+; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-ON-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_intrinsic_f64:
+; SOFT-FLOAT-FPC-FAST: # %bb.0:
+; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
+ %result = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
+ ret double %result
+}
+
+define float @fmuladd_contract_f32(float %a, float %b, float %c) #0 {
+; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_contract_f32:
+; SOFT-FLOAT-FPC-OFF: # %bb.0:
+; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-OFF-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_contract_f32:
+; SOFT-FLOAT-FPC-ON: # %bb.0:
+; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-ON-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_contract_f32:
+; SOFT-FLOAT-FPC-FAST: # %bb.0:
+; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r2, %r2
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r3
+; SOFT-FLOAT-FPC-FAST-NEXT: lr %r13, %r4
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __mulsf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r13
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __addsf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
+ %product = fmul float %a, %b
+ %result = fadd float %product, %c
+ ret float %result
+}
+
+define double @fmuladd_contract_f64(double %a, double %b, double %c) #0 {
+; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_contract_f64:
+; SOFT-FLOAT-FPC-OFF: # %bb.0:
+; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_contract_f64:
+; SOFT-FLOAT-FPC-ON: # %bb.0:
+; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-ON-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-ON-NEXT: br %r14
+;
+; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_contract_f64:
+; SOFT-FLOAT-FPC-FAST: # %bb.0:
+; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
+; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
+; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r13, %r4
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __muldf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r3, %r13
+; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __adddf3 at PLT
+; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
+; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
+ %product = fmul double %a, %b
+ %result = fadd double %product, %c
+ ret double %result
+}
+
----------------
arsenm wrote:
Should test some vector cases too
https://github.com/llvm/llvm-project/pull/106615
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