[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

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git-clang-format --diff 1fc3ca1a121e4ae7d0cc35ee314d3aa4b8c98361 a209293f21be1c692b2a0692feb651bf96d72c4d --extensions cpp -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVCallingConv.cpp llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 20c9c1b703..64e03d86f3 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -421,7 +421,8 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
             .addImm(RegImm.Imm);
       } else if (RISCV::GPRRegClass.contains(RegImm.Reg)) {
         assert(RegImm.Imm == 0);
-        BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::PseudoMV_FPR16INX), NewReg)
+        BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::PseudoMV_FPR16INX),
+                NewReg)
             .addReg(RegImm.Reg);
       } else {
         // If we are looking at replacing an FPR register we don't expect to

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https://github.com/llvm/llvm-project/pull/107446