[llvm] a9e05a3 - [ARM] Use MCRegister for ARMTargetStreamer::emitRegSave. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 14 18:01:20 PDT 2024
Author: Craig Topper
Date: 2024-09-14T17:25:56-07:00
New Revision: a9e05a36dbbbfc549434427fdde346c107500def
URL: https://github.com/llvm/llvm-project/commit/a9e05a36dbbbfc549434427fdde346c107500def
DIFF: https://github.com/llvm/llvm-project/commit/a9e05a36dbbbfc549434427fdde346c107500def.diff
LOG: [ARM] Use MCRegister for ARMTargetStreamer::emitRegSave. NFC
Added:
Modified:
llvm/include/llvm/MC/MCStreamer.h
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index 78aa12062102c2..42b1114266adb7 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -148,7 +148,7 @@ class ARMTargetStreamer : public MCTargetStreamer {
int64_t Offset = 0);
virtual void emitMovSP(unsigned Reg, int64_t Offset = 0);
virtual void emitPad(int64_t Offset);
- virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
+ virtual void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
bool isVector);
virtual void emitUnwindRaw(int64_t StackOffset,
const SmallVectorImpl<uint8_t> &Opcodes);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 710182985a1e9e..1105a96b295ced 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1219,7 +1219,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
assert(DstReg == ARM::SP &&
"Only stack pointer as a destination reg is supported");
- SmallVector<unsigned, 4> RegList;
+ SmallVector<MCRegister, 4> RegList;
// Skip src & dst reg, and pred ops.
unsigned StartOp = 2 + 2;
// Use all the operands.
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 66b99f64d9d430..3e3f134d347016 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -808,7 +808,7 @@ class ARMOperand : public MCParsedAsmOperand {
} Kind;
SMLoc StartLoc, EndLoc, AlignmentLoc;
- SmallVector<unsigned, 8> Registers;
+ SmallVector<MCRegister, 8> Registers;
ARMAsmParser *Parser;
@@ -1005,7 +1005,7 @@ class ARMOperand : public MCParsedAsmOperand {
return Reg.RegNum;
}
- const SmallVectorImpl<unsigned> &getRegList() const {
+ const SmallVectorImpl<MCRegister> &getRegList() const {
assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
Kind == k_FPSRegisterListWithVPR ||
@@ -2630,15 +2630,15 @@ class ARMOperand : public MCParsedAsmOperand {
void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- const SmallVectorImpl<unsigned> &RegList = getRegList();
- for (unsigned Reg : RegList)
+ const SmallVectorImpl<MCRegister> &RegList = getRegList();
+ for (MCRegister Reg : RegList)
Inst.addOperand(MCOperand::createReg(Reg));
}
void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- const SmallVectorImpl<unsigned> &RegList = getRegList();
- for (unsigned Reg : RegList)
+ const SmallVectorImpl<MCRegister> &RegList = getRegList();
+ for (MCRegister Reg : RegList)
Inst.addOperand(MCOperand::createReg(Reg));
}
@@ -4103,7 +4103,7 @@ void ARMOperand::print(raw_ostream &OS) const {
case k_FPDRegisterListWithVPR: {
OS << "<register_list ";
- const SmallVectorImpl<unsigned> &RegList = getRegList();
+ const SmallVectorImpl<MCRegister> &RegList = getRegList();
for (auto I = RegList.begin(), E = RegList.end(); I != E;) {
OS << RegName(*I);
if (++I < E) OS << ", ";
@@ -12519,7 +12519,7 @@ bool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) {
ARMOperand &Op = (ARMOperand &)*Operands[0];
if (!Op.isRegList())
return Error(L, ".seh_save_regs{_w} expects GPR registers");
- const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
+ const SmallVectorImpl<MCRegister> &RegList = Op.getRegList();
uint32_t Mask = 0;
for (size_t i = 0; i < RegList.size(); ++i) {
unsigned Reg = MRI->getEncodingValue(RegList[i]);
@@ -12561,7 +12561,7 @@ bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) {
ARMOperand &Op = (ARMOperand &)*Operands[0];
if (!Op.isDPRRegList())
return Error(L, ".seh_save_fregs expects DPR registers");
- const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
+ const SmallVectorImpl<MCRegister> &RegList = Op.getRegList();
uint32_t Mask = 0;
for (size_t i = 0; i < RegList.size(); ++i) {
unsigned Reg = MRI->getEncodingValue(RegList[i]);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index c9631bd7c7aac5..ff2b557090bc72 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -83,7 +83,7 @@ class ARMTargetAsmStreamer : public ARMTargetStreamer {
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
void emitPad(int64_t Offset) override;
- void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
+ void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
bool isVector) override;
void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override;
@@ -165,8 +165,8 @@ void ARMTargetAsmStreamer::emitPad(int64_t Offset) {
OS << "\t.pad\t#" << Offset << '\n';
}
-void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
- bool isVector) {
+void ARMTargetAsmStreamer::emitRegSave(
+ const SmallVectorImpl<MCRegister> &RegList, bool isVector) {
assert(RegList.size() && "RegList should not be empty");
if (isVector)
OS << "\t.vsave\t{";
@@ -404,7 +404,7 @@ class ARMTargetELFStreamer : public ARMTargetStreamer {
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
void emitPad(int64_t Offset) override;
- void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
+ void emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
bool isVector) override;
void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override;
@@ -472,7 +472,7 @@ class ARMELFStreamer : public MCELFStreamer {
void emitSetFP(unsigned NewFpReg, unsigned NewSpReg, int64_t Offset = 0);
void emitMovSP(unsigned Reg, int64_t Offset = 0);
void emitPad(int64_t Offset);
- void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
+ void emitRegSave(const SmallVectorImpl<MCRegister> &RegList, bool isVector);
void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes);
void emitFill(const MCExpr &NumBytes, uint64_t FillValue,
SMLoc Loc) override {
@@ -766,8 +766,8 @@ void ARMTargetELFStreamer::emitPad(int64_t Offset) {
getStreamer().emitPad(Offset);
}
-void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
- bool isVector) {
+void ARMTargetELFStreamer::emitRegSave(
+ const SmallVectorImpl<MCRegister> &RegList, bool isVector) {
getStreamer().emitRegSave(RegList, isVector);
}
@@ -1412,17 +1412,17 @@ void ARMELFStreamer::emitPad(int64_t Offset) {
static std::pair<unsigned, unsigned>
collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx,
- const SmallVectorImpl<unsigned> &RegList, bool IsVector,
+ const SmallVectorImpl<MCRegister> &RegList, bool IsVector,
uint32_t &Mask_) {
uint32_t Mask = 0;
unsigned Count = 0;
while (Idx > 0) {
- unsigned Reg = RegList[Idx - 1];
+ MCRegister Reg = RegList[Idx - 1];
if (Reg == ARM::RA_AUTH_CODE)
break;
- Reg = MRI.getEncodingValue(Reg);
- assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
- unsigned Bit = (1u << Reg);
+ unsigned RegEnc = MRI.getEncodingValue(Reg);
+ assert(RegEnc < (IsVector ? 32U : 16U) && "Register out of range");
+ unsigned Bit = (1u << RegEnc);
if ((Mask & Bit) == 0) {
Mask |= Bit;
++Count;
@@ -1434,7 +1434,7 @@ collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx,
return {Idx, Count};
}
-void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
+void ARMELFStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
bool IsVector) {
uint32_t Mask;
unsigned Idx, Count;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index 1237e50c22fdce..d550b70d8e5919 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
@@ -96,7 +96,7 @@ void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
int64_t Offset) {}
void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
void ARMTargetStreamer::emitPad(int64_t Offset) {}
-void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
+void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
bool isVector) {}
void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
const SmallVectorImpl<uint8_t> &Opcodes) {
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