[llvm] f427028 - [ARM] Use MCRegister in more places. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 14 17:00:08 PDT 2024
Author: Craig Topper
Date: 2024-09-14T16:55:43-07:00
New Revision: f427028d62d27b440e1c2821b4781ddb399b61db
URL: https://github.com/llvm/llvm-project/commit/f427028d62d27b440e1c2821b4781ddb399b61db
DIFF: https://github.com/llvm/llvm-project/commit/f427028d62d27b440e1c2821b4781ddb399b61db.diff
LOG: [ARM] Use MCRegister in more places. NFC
Added:
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 10fef901f77181..66b99f64d9d430 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -759,7 +759,7 @@ class ARMAsmParser : public MCTargetAsmParser {
bool hasMVE() const { return getSTI().hasFeature(ARM::HasMVEIntegerOps); }
// Return the low-subreg of a given Q register.
- unsigned getDRegFromQReg(unsigned QReg) const {
+ MCRegister getDRegFromQReg(MCRegister QReg) const {
return MRI->getSubReg(QReg, ARM::dsub_0);
}
@@ -862,12 +862,12 @@ class ARMOperand : public MCParsedAsmOperand {
};
struct RegOp {
- unsigned RegNum;
+ MCRegister RegNum;
};
// A vector register list is a sequential list of 1 to 4 registers.
struct VectorListOp {
- unsigned RegNum;
+ MCRegister RegNum;
unsigned Count;
unsigned LaneIndex;
bool isDoubleSpaced;
@@ -883,11 +883,11 @@ class ARMOperand : public MCParsedAsmOperand {
/// Combined record for all forms of ARM address expressions.
struct MemoryOp {
- unsigned BaseRegNum;
+ MCRegister BaseRegNum;
// Offset is in OffsetReg or OffsetImm. If both are zero, no offset
// was specified.
const MCExpr *OffsetImm; // Offset immediate value
- unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
+ MCRegister OffsetRegNum; // Offset register num, when OffsetImm == NULL
ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
unsigned ShiftImm; // shift for OffsetReg.
unsigned Alignment; // 0 = no alignment specified
@@ -896,7 +896,7 @@ class ARMOperand : public MCParsedAsmOperand {
};
struct PostIdxRegOp {
- unsigned RegNum;
+ MCRegister RegNum;
bool isAdd;
ARM_AM::ShiftOpc ShiftTy;
unsigned ShiftImm;
@@ -909,14 +909,14 @@ class ARMOperand : public MCParsedAsmOperand {
struct RegShiftedRegOp {
ARM_AM::ShiftOpc ShiftTy;
- unsigned SrcReg;
- unsigned ShiftReg;
+ MCRegister SrcReg;
+ MCRegister ShiftReg;
unsigned ShiftImm;
};
struct RegShiftedImmOp {
ARM_AM::ShiftOpc ShiftTy;
- unsigned SrcReg;
+ MCRegister SrcReg;
unsigned ShiftImm;
};
@@ -2547,9 +2547,9 @@ class ARMOperand : public MCParsedAsmOperand {
void addVPTPredROperands(MCInst &Inst, unsigned N) const {
assert(N == 4 && "Invalid number of operands!");
addVPTPredNOperands(Inst, N-1);
- unsigned RegNum;
+ MCRegister RegNum;
if (getVPTPred() == ARMVCC::None) {
- RegNum = 0;
+ RegNum = MCRegister();
} else {
unsigned NextOpIndex = Inst.getNumOperands();
auto &MCID = Parser->getInstrDesc(Inst.getOpcode());
@@ -3393,7 +3393,7 @@ class ARMOperand : public MCParsedAsmOperand {
else if (isDReg() && !Parser->hasMVE()) {
Inst.addOperand(MCOperand::createReg(Reg.RegNum));
} else if (isQReg() && !Parser->hasMVE()) {
- auto DPair = Parser->getDRegFromQReg(Reg.RegNum);
+ MCRegister DPair = Parser->getDRegFromQReg(Reg.RegNum);
DPair = Parser->getMRI()->getMatchingSuperReg(
DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
Inst.addOperand(MCOperand::createReg(DPair));
@@ -3684,10 +3684,10 @@ class ARMOperand : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S,
+ static std::unique_ptr<ARMOperand> CreateCCOut(MCRegister Reg, SMLoc S,
ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_CCOut, Parser);
- Op->Reg.RegNum = RegNum;
+ Op->Reg.RegNum = Reg;
Op->StartLoc = S;
Op->EndLoc = S;
return Op;
@@ -3703,19 +3703,19 @@ class ARMOperand : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
- SMLoc E, ARMAsmParser &Parser) {
+ static std::unique_ptr<ARMOperand> CreateReg(MCRegister Reg, SMLoc S, SMLoc E,
+ ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_Register, Parser);
- Op->Reg.RegNum = RegNum;
+ Op->Reg.RegNum = Reg;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
}
static std::unique_ptr<ARMOperand>
- CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
- unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E,
- ARMAsmParser &Parser) {
+ CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg,
+ MCRegister ShiftReg, unsigned ShiftImm, SMLoc S,
+ SMLoc E, ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister, Parser);
Op->RegShiftedReg.ShiftTy = ShTy;
Op->RegShiftedReg.SrcReg = SrcReg;
@@ -3727,7 +3727,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
+ CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, MCRegister SrcReg,
unsigned ShiftImm, SMLoc S, SMLoc E,
ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate, Parser);
@@ -3793,7 +3793,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
+ CreateRegList(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs,
SMLoc StartLoc, SMLoc EndLoc, ARMAsmParser &Parser) {
assert(Regs.size() > 0 && "RegList contains no registers?");
KindTy Kind = k_RegisterList;
@@ -3827,10 +3827,10 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
- SMLoc S, SMLoc E, ARMAsmParser &Parser) {
+ CreateVectorList(MCRegister Reg, unsigned Count, bool isDoubleSpaced, SMLoc S,
+ SMLoc E, ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_VectorList, Parser);
- Op->VectorList.RegNum = RegNum;
+ Op->VectorList.RegNum = Reg;
Op->VectorList.Count = Count;
Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Op->StartLoc = S;
@@ -3839,10 +3839,10 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
+ CreateVectorListAllLanes(MCRegister Reg, unsigned Count, bool isDoubleSpaced,
SMLoc S, SMLoc E, ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes, Parser);
- Op->VectorList.RegNum = RegNum;
+ Op->VectorList.RegNum = Reg;
Op->VectorList.Count = Count;
Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Op->StartLoc = S;
@@ -3884,14 +3884,14 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
+ CreateMem(MCRegister BaseReg, const MCExpr *OffsetImm, MCRegister OffsetReg,
ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
bool isNegative, SMLoc S, SMLoc E, ARMAsmParser &Parser,
SMLoc AlignmentLoc = SMLoc()) {
auto Op = std::make_unique<ARMOperand>(k_Memory, Parser);
- Op->Memory.BaseRegNum = BaseRegNum;
+ Op->Memory.BaseRegNum = BaseReg;
Op->Memory.OffsetImm = OffsetImm;
- Op->Memory.OffsetRegNum = OffsetRegNum;
+ Op->Memory.OffsetRegNum = OffsetReg;
Op->Memory.ShiftType = ShiftType;
Op->Memory.ShiftImm = ShiftImm;
Op->Memory.Alignment = Alignment;
@@ -3903,10 +3903,10 @@ class ARMOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<ARMOperand>
- CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
+ CreatePostIdxReg(MCRegister Reg, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
unsigned ShiftImm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister, Parser);
- Op->PostIdxReg.RegNum = RegNum;
+ Op->PostIdxReg.RegNum = Reg;
Op->PostIdxReg.isAdd = isAdd;
Op->PostIdxReg.ShiftTy = ShiftTy;
Op->PostIdxReg.ShiftImm = ShiftImm;
@@ -4104,8 +4104,7 @@ void ARMOperand::print(raw_ostream &OS) const {
OS << "<register_list ";
const SmallVectorImpl<unsigned> &RegList = getRegList();
- for (SmallVectorImpl<unsigned>::const_iterator
- I = RegList.begin(), E = RegList.end(); I != E; ) {
+ for (auto I = RegList.begin(), E = RegList.end(); I != E;) {
OS << RegName(*I);
if (++I < E) OS << ", ";
}
@@ -4311,11 +4310,11 @@ int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
(ARMOperand *)Operands.pop_back_val().release());
if (!PrevOp->isReg())
return Error(PrevOp->getStartLoc(), "shift must be of a register");
- int SrcReg = PrevOp->getReg();
+ MCRegister SrcReg = PrevOp->getReg();
SMLoc EndLoc;
int64_t Imm = 0;
- int ShiftReg = 0;
+ MCRegister ShiftReg;
if (ShiftTy == ARM_AM::rrx) {
// RRX Doesn't have an explicit shift amount. The encoder expects
// the shift register to be the same as the source register. Seems odd,
@@ -4591,8 +4590,8 @@ static unsigned getNextRegister(unsigned Reg) {
// Insert an <Encoding, Register> pair in an ordered vector. Return true on
// success, or false, if duplicate encoding found.
static bool
-insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
- unsigned Enc, unsigned Reg) {
+insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs,
+ unsigned Enc, MCRegister Reg) {
Regs.emplace_back(Enc, Reg);
for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
if (J->first == Enc) {
@@ -4626,7 +4625,7 @@ bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
// The reglist instructions have at most 16 registers, so reserve
// space for that many.
int EReg = 0;
- SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
+ SmallVector<std::pair<unsigned, MCRegister>, 16> Registers;
// Allow Q regs and just interpret them as the two D sub-registers.
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
@@ -7409,9 +7408,9 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
// Adjust only if Op1 is a GPR.
if (Op1.isReg() && MRC.contains(Op1.getReg())) {
- unsigned Reg1 = Op1.getReg();
+ MCRegister Reg1 = Op1.getReg();
unsigned Rt = MRI->getEncodingValue(Reg1);
- unsigned Reg2 = Op2.getReg();
+ MCRegister Reg2 = Op2.getReg();
unsigned Rt2 = MRI->getEncodingValue(Reg2);
// Rt2 must be Rt + 1.
if (Rt + 1 != Rt2)
@@ -7426,7 +7425,7 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
IsLoad ? "destination operands must start start at an even register"
: "source operands must start start at an even register");
- unsigned NewReg = MRI->getMatchingSuperReg(
+ MCRegister NewReg = MRI->getMatchingSuperReg(
Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
Operands[Idx] = ARMOperand::CreateReg(NewReg, Op1.getStartLoc(),
Op2.getEndLoc(), *this);
@@ -7464,7 +7463,7 @@ static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
bool &containsReg) {
containsReg = false;
for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
- unsigned OpReg = Inst.getOperand(i).getReg();
+ MCRegister OpReg = Inst.getOperand(i).getReg();
if (OpReg == Reg)
containsReg = true;
// Anything other than a low register isn't legal here.
@@ -7776,7 +7775,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
return true;
break;
case ARM::t2BXJ: {
- const unsigned RmReg = Inst.getOperand(0).getReg();
+ const MCRegister RmReg = Inst.getOperand(0).getReg();
// Rm = SP is no longer unpredictable in v8-A
if (RmReg == ARM::SP && !hasV8Ops())
return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
@@ -8054,7 +8053,7 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
//
// Thumb LDM instructions are writeback iff the base register is not
// in the register list.
- unsigned Rn = Inst.getOperand(0).getReg();
+ MCRegister Rn = Inst.getOperand(0).getReg();
bool HasWritebackToken =
(static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
.isToken() &&
@@ -8508,8 +8507,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::t2SMLSLD:
case ARM::t2SMLSLDX:
case ARM::t2SMULL: {
- unsigned RdHi = Inst.getOperand(0).getReg();
- unsigned RdLo = Inst.getOperand(1).getReg();
+ MCRegister RdHi = Inst.getOperand(0).getReg();
+ MCRegister RdLo = Inst.getOperand(1).getReg();
if(RdHi == RdLo) {
return Error(Loc,
"unpredictable instruction, RdHi and RdLo must be
diff erent");
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index cbbe771d7f23e5..9f6bc31f8aa030 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -1188,7 +1188,7 @@ uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
MCRegister CFARegister = ARM::SP;
int CFARegisterOffset = 0;
// Mark savable registers as initially unsaved
- DenseMap<unsigned, int> RegOffsets;
+ DenseMap<MCRegister, int> RegOffsets;
int FloatRegCount = 0;
// Process each .cfi directive and build up compact unwind info.
for (const MCCFIInstruction &Inst : Instrs) {
@@ -1332,7 +1332,7 @@ uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
// Floating point registers must either be saved sequentially, or we defer to
// DWARF. No gaps allowed here so check that each saved d-register is
// precisely where it should be.
- static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
+ static MCPhysReg FPRCSRegs[] = {ARM::D8, ARM::D10, ARM::D12, ARM::D14};
for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
if (Offset == RegOffsets.end()) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
index 35c2d6c5dea153..e56cb028c4e25f 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
@@ -157,9 +157,9 @@ namespace ARM_ISB {
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
///
-static inline bool isARMLowRegister(unsigned Reg) {
+static inline bool isARMLowRegister(MCRegister Reg) {
using namespace ARM;
- switch (Reg) {
+ switch (Reg.id()) {
case R0: case R1: case R2: case R3:
case R4: case R5: case R6: case R7:
return true;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 24e627cd9a4e1f..8a7339fd936b91 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -260,7 +260,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
case ARM::tLDMIA: {
bool Writeback = true;
- unsigned BaseReg = MI->getOperand(0).getReg();
+ MCRegister BaseReg = MI->getOperand(0).getReg();
for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
if (MI->getOperand(i).getReg() == BaseReg)
Writeback = false;
@@ -291,7 +291,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
case ARM::STLEXD: {
const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
- unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
+ MCRegister Reg = MI->getOperand(isStore ? 1 : 0).getReg();
if (MRC.contains(Reg)) {
MCInst NewMI;
MCOperand NewReg;
@@ -342,7 +342,7 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
printRegName(O, Reg);
} else if (Op.isImm()) {
markup(O, Markup::Immediate) << '#' << formatImm(Op.getImm());
@@ -871,7 +871,7 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
O << ", ";
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
@@ -1141,7 +1141,7 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
WithMarkup ScopedMarkup = markup(O, Markup::Memory);
O << "[";
printRegName(O, MO1.getReg());
- if (unsigned RegNum = MO2.getReg()) {
+ if (MCRegister RegNum = MO2.getReg()) {
O << ", ";
printRegName(O, RegNum);
}
@@ -1208,7 +1208,7 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
const MCOperand &MO1 = MI->getOperand(OpNum);
const MCOperand &MO2 = MI->getOperand(OpNum + 1);
- unsigned Reg = MO1.getReg();
+ MCRegister Reg = MO1.getReg();
printRegName(O, Reg);
// Print the shift opc.
@@ -1490,9 +1490,9 @@ void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
- unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
- unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
+ MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
O << "{";
printRegName(O, Reg0);
O << ", ";
@@ -1503,9 +1503,9 @@ void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
- unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
- unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
+ MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
O << "{";
printRegName(O, Reg0);
O << ", ";
@@ -1558,9 +1558,9 @@ void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
- unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
- unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
+ MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
O << "{";
printRegName(O, Reg0);
O << "[], ";
@@ -1605,9 +1605,9 @@ void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
- unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
- unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
+ MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
O << "{";
printRegName(O, Reg0);
O << "[], ";
@@ -1684,7 +1684,7 @@ template<unsigned NumRegs>
void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
const char *Prefix = "{";
for (unsigned i = 0; i < NumRegs; i++) {
O << Prefix;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 3f37acff292b4b..92427b41f0bb3d 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -543,7 +543,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ MCRegister Reg = MO.getReg();
unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
// In NEON, Q registers are encoded as 2x their register number,
@@ -555,7 +555,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
if (STI.hasFeature(ARM::HasMVEIntegerOps))
return RegNo;
- switch (Reg) {
+ switch (Reg.id()) {
default:
return RegNo;
case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
@@ -711,7 +711,7 @@ static bool HasConditionalBranch(const MCInst &MI) {
const MCOperand &MCOp1 = MI.getOperand(i);
const MCOperand &MCOp2 = MI.getOperand(i + 1);
if (MCOp1.isImm() && MCOp2.isReg() &&
- (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
+ (!MCOp2.getReg() || MCOp2.getReg() == ARM::CPSR)) {
if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
return true;
}
@@ -1311,7 +1311,7 @@ getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
unsigned Imm = MO1.getImm();
bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
- bool isReg = MO.getReg() != 0;
+ bool isReg = MO.getReg().isValid();
uint32_t Binary = ARM_AM::getAM2Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
if (isReg) {
@@ -1347,7 +1347,7 @@ getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
unsigned Imm = MO1.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
- bool isImm = MO.getReg() == 0;
+ bool isImm = !MO.getReg().isValid();
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
@@ -1383,7 +1383,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
unsigned Imm = MO2.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
- bool isImm = MO1.getReg() == 0;
+ bool isImm = !MO1.getReg().isValid();
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
@@ -1537,7 +1537,7 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
// Encode the shift opcode.
unsigned SBits = 0;
- unsigned Rs = MO1.getReg();
+ MCRegister Rs = MO1.getReg();
if (Rs) {
// Set shift operand (bit[7:4]).
// LSL - 0001
@@ -1737,7 +1737,7 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
//
// LDM/STM:
// {15-0} = Bitfield of GPRs.
- unsigned Reg = MI.getOperand(Op).getReg();
+ MCRegister Reg = MI.getOperand(Op).getReg();
bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
@@ -1851,7 +1851,8 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(Op);
- if (MO.getReg() == 0) return 0x0D;
+ if (!MO.getReg())
+ return 0x0D;
return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index cf4fc37f84553e..01a271327049f1 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -111,7 +111,7 @@ static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
bool ListContainsPC = false, ListContainsLR = false;
for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
assert(MI.getOperand(OI).isReg() && "expected register");
- switch (MI.getOperand(OI).getReg()) {
+ switch (MI.getOperand(OI).getReg().id()) {
default:
break;
case ARM::LR:
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