[llvm] [SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands. (PR #107273)

[Philip Reames via llvm-commits]

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@@ -1223,6 +1237,22 @@ static bool doesNotNeedToSchedule(ArrayRef<Value *> VL) {
          (all_of(VL, isUsedOutsideBlock) || all_of(VL, areAllOperandsNonInsts));
 }
 
+/// Returns true if widened type of \p Ty elements with size \p Sz represents
+/// full vector type, i.e. adding extra element results in extra parts upon type
+/// legalization.
+static bool hasFullVectorsOnly(const TargetTransformInfo &TTI, Type *Ty,
+                               unsigned Sz) {
+  if (Sz <= 1)
+    return false;
+  if (!isValidElementType(Ty) && !isa<FixedVectorType>(Ty))
+    return false;
+  if (has_single_bit(Sz))
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preames wrote:

I don't think there's any requirement that a power of two VL is a full register?  Consider SEW=64, VL=2 on RISCV.  With zvl256b this is at most half of a register.  At zvl128b, it *might* be a full register (or might not.)

https://github.com/llvm/llvm-project/pull/107273