[llvm] [NFC] Update function names in MCTargetAsmParser.h (PR #108643)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 13 13:32:09 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-amdgpu
Author: Lei Huang (lei137)
<details>
<summary>Changes</summary>
Update function names to adhere to LLVM coding standard.
---
Patch is 62.33 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108643.diff
21 Files Affected:
- (modified) llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h (+7-7)
- (modified) llvm/lib/MC/MCParser/AsmParser.cpp (+3-3)
- (modified) llvm/lib/MC/MCParser/MCTargetAsmParser.cpp (+3-3)
- (modified) llvm/lib/MC/MCParser/MasmParser.cpp (+3-3)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+8-8)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+7-7)
- (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (+8-8)
- (modified) llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp (+5-5)
- (modified) llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (+8-8)
- (modified) llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp (+5-5)
- (modified) llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (+7-7)
- (modified) llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (+62-62)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+7-7)
- (modified) llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (+5-5)
- (modified) llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp (+4-4)
- (modified) llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp (+2-2)
- (modified) llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp (+8-8)
``````````diff
diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
index 49ce417e6fbb20..93e27a02aeffcb 100644
--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -439,14 +439,14 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// \param Operands [out] - The list of parsed operands, this returns
/// ownership of them to the caller.
/// \return True on failure.
- virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ virtual bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) = 0;
- virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ virtual bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
AsmToken Token, OperandVector &Operands) {
- return ParseInstruction(Info, Name, Token.getLoc(), Operands);
+ return parseInstruction(Info, Name, Token.getLoc(), Operands);
}
- /// ParseDirective - Parse a target specific assembler directive
+ /// parseDirectives - Parse a target specific assembler directive
/// This method is deprecated, use 'parseDirective' instead.
///
/// The parser is positioned following the directive name. The target
@@ -457,7 +457,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// end-of-statement token and false is returned.
///
/// \param DirectiveID - the identifier token of the directive.
- virtual bool ParseDirective(AsmToken DirectiveID) { return true; }
+ virtual bool parseDirectives(AsmToken DirectiveID) { return true; }
/// Parses a target-specific assembler directive.
///
@@ -477,13 +477,13 @@ class MCTargetAsmParser : public MCAsmParserExtension {
///
/// On failure, the target parser is responsible for emitting a diagnostic
/// explaining the match failure.
- virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ virtual bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) = 0;
/// Allows targets to let registers opt out of clobber lists.
- virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
+ virtual bool omitRegisterFromClobberLists(unsigned RegNo) { return false; }
/// Allow a target to add special case operand matching for things that
/// tblgen doesn't/can't handle effectively. For example, literal
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index 66e52fe2d08f8d..9eff35642c9f39 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -2322,7 +2322,7 @@ bool AsmParser::parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
// Canonicalize the opcode to lower case.
std::string OpcodeStr = IDVal.lower();
ParseInstructionInfo IInfo(Info.AsmRewrites);
- bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+ bool ParseHadError = getTargetParser().parseInstruction(IInfo, OpcodeStr, ID,
Info.ParsedOperands);
Info.ParseError = ParseHadError;
@@ -2379,7 +2379,7 @@ bool AsmParser::parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
// If parsing succeeded, match the instruction.
if (!ParseHadError) {
uint64_t ErrorInfo;
- if (getTargetParser().MatchAndEmitInstruction(
+ if (getTargetParser().matchAndEmitInstruction(
IDLoc, Info.Opcode, Info.ParsedOperands, Out, ErrorInfo,
getTargetParser().isParsingMSInlineAsm()))
return true;
@@ -6029,7 +6029,7 @@ bool AsmParser::parseMSInlineAsm(
// Register operand.
if (Operand.isReg() && !Operand.needAddressOf() &&
- !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
+ !getTargetParser().omitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs();
// Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs)
diff --git a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
index 665d92eb9a21c5..931d5888c9034c 100644
--- a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
@@ -31,15 +31,15 @@ const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
ParseStatus MCTargetAsmParser::parseDirective(AsmToken DirectiveID) {
SMLoc StartTokLoc = getTok().getLoc();
- // Delegate to ParseDirective by default for transition period. Once the
+ // Delegate to parseDirectives by default for transition period. Once the
// transition is over, this method should just return NoMatch.
- bool Res = ParseDirective(DirectiveID);
+ bool Res = parseDirectives(DirectiveID);
// Some targets erroneously report success after emitting an error.
if (getParser().hasPendingError())
return ParseStatus::Failure;
- // ParseDirective returns true if there was an error or if the directive is
+ // parseDirectives returns true if there was an error or if the directive is
// not target-specific. Disambiguate the two cases by comparing position of
// the lexer before and after calling the method: if no tokens were consumed,
// there was no match, otherwise there was a failure.
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp
index 9f619c5018b509..0c64af9e460ea0 100644
--- a/llvm/lib/MC/MCParser/MasmParser.cpp
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp
@@ -2657,7 +2657,7 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info,
// Canonicalize the opcode to lower case.
std::string OpcodeStr = IDVal.lower();
ParseInstructionInfo IInfo(Info.AsmRewrites);
- bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+ bool ParseHadError = getTargetParser().parseInstruction(IInfo, OpcodeStr, ID,
Info.ParsedOperands);
Info.ParseError = ParseHadError;
@@ -2714,7 +2714,7 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info,
// If parsing succeeded, match the instruction.
if (!ParseHadError) {
uint64_t ErrorInfo;
- if (getTargetParser().MatchAndEmitInstruction(
+ if (getTargetParser().matchAndEmitInstruction(
IDLoc, Info.Opcode, Info.ParsedOperands, Out, ErrorInfo,
getTargetParser().isParsingMSInlineAsm()))
return true;
@@ -7389,7 +7389,7 @@ bool MasmParser::parseMSInlineAsm(
// Register operand.
if (Operand.isReg() && !Operand.needAddressOf() &&
- !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
+ !getTargetParser().omitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs();
// Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 13a7eef4788524..72c51f5ab09a61 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -231,7 +231,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
SmallVectorImpl<SMLoc> &Loc);
unsigned getNumRegsForRegKind(RegKind K);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -321,12 +321,12 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool areEqualRegs(const MCParsedAsmOperand &Op1,
const MCParsedAsmOperand &Op2) const override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -5086,9 +5086,9 @@ bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
return false;
}
-/// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
+/// parseInstruction - Parse an AArch64 instruction mnemonic followed by its
/// operands.
-bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
Name = StringSwitch<StringRef>(Name.lower())
@@ -6205,7 +6205,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
static const char *getSubtargetFeatureName(uint64_t Val);
-bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -6798,8 +6798,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// ParseDirective parses the arm specific directives
-bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the arm specific directives
+bool AArch64AsmParser::parseDirectives(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 5db6c52d189e37..51de0f8ffb12d9 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1256,7 +1256,7 @@ class KernelScopeInfo {
}
void usesAgprAt(int i) {
- // Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction
+ // Instruction will error in AMDGPUAsmParser::matchAndEmitInstruction
if (!hasMAIInsts(*MSTI))
return;
@@ -1597,15 +1597,15 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
OperandMode Mode = OperandMode_Default);
StringRef parseMnemonicSuffix(StringRef Name);
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
//bool ProcessInstruction(MCInst &Inst);
@@ -5288,7 +5288,7 @@ static bool isInvalidVOPDY(const OperandVector &Operands,
return false;
}
-bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -6194,7 +6194,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
return false;
}
-bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool AMDGPUAsmParser::parseDirectives(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getString();
if (isHsaAbi(getSTI())) {
@@ -6393,7 +6393,7 @@ static void applyMnemonicAliases(StringRef &Mnemonic,
const FeatureBitset &Features,
unsigned VariantID);
-bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AMDGPUAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// Add the instruction mnemonic
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 10fef901f77181..9dbc93f38e4f3a 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -712,9 +712,9 @@ class ARMAsmParser : public MCTargetAsmParser {
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -723,7 +723,7 @@ class ARMAsmParser : public MCTargetAsmParser {
checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -7052,7 +7052,7 @@ void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
}
/// Parse an arm instruction mnemonic followed by its operands.
-bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
MCAsmParser &Parser = getParser();
@@ -11351,7 +11351,7 @@ static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
unsigned VariantID = 0);
static const char *getSubtargetFeatureName(uint64_t Val);
-bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool ARMAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -11428,8 +11428,8 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// parseDirective parses the arm specific directives
-bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the arm specific directives
+bool ARMAsmParser::parseDirectives(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
@@ -12121,7 +12121,7 @@ bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
return false;
}
-/// parseDirective
+/// parseDirectivePad
/// ::= .pad offset
bool ARMAsmParser::parseDirectivePad(SMLoc L) {
MCAsmParser &Parser = getParser();
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index c016b2dd91dc67..845441aa910725 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -51,7 +51,7 @@ class AVRAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "AVRGenAsmMatcher.inc"
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -60,7 +60,7 @@ class AVRAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -320,7 +320,7 @@ bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
return false;
}
-bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
+bool AVRAsmParser::matchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -623,7 +623,7 @@ void AVRAsmParser::eatComma() {
}
}
-bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AVRAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Mnemonic, SMLoc NameLoc,
OperandVector &Operands) {
Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
index 9672ed009e9be1..98ab0f2bd399b5 100644
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
@@ -34,7 +34,7 @@ class BPFAsmParser : public MCTargetAsmParser {
bool PreMatchCheck(OperandVector &Operands);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -43,7 +43,7 @@ class BPFAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
// "=" is used as assignment operator for assembly statment, so can't be used
@@ -304,7 +304,7 @@ bool BPFAsmParser::PreMatchCheck(OperandVector &Operands) {
return false;
}
-bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool BPFAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/108643
More information about the llvm-commits
mailing list