[llvm] 57aaf5e - [RISCV] Use MCRegister in RISCVMCInstrAnalysis. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 23:36:28 PDT 2024
Author: Craig Topper
Date: 2024-09-12T23:35:55-07:00
New Revision: 57aaf5ec9fbcf736daf742d2cbcf103b6df65881
URL: https://github.com/llvm/llvm-project/commit/57aaf5ec9fbcf736daf742d2cbcf103b6df65881
DIFF: https://github.com/llvm/llvm-project/commit/57aaf5ec9fbcf736daf742d2cbcf103b6df65881.diff
LOG: [RISCV] Use MCRegister in RISCVMCInstrAnalysis. NFC
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 53329af093de0f..a0dc9d93c84b8d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -126,16 +126,16 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
- static bool isGPR(unsigned Reg) {
+ static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
}
- static unsigned getRegIndex(unsigned Reg) {
+ static unsigned getRegIndex(MCRegister Reg) {
assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
return Reg - RISCV::X1;
}
- void setGPRState(unsigned Reg, std::optional<int64_t> Value) {
+ void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {
if (Reg == RISCV::X0)
return;
@@ -149,7 +149,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
}
- std::optional<int64_t> getGPRState(unsigned Reg) const {
+ std::optional<int64_t> getGPRState(MCRegister Reg) const {
if (Reg == RISCV::X0)
return 0;
@@ -301,7 +301,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
private:
- static bool maybeReturnAddress(unsigned Reg) {
+ static bool maybeReturnAddress(MCRegister Reg) {
// X1 is used for normal returns, X5 for returns from outlined functions.
return Reg == RISCV::X1 || Reg == RISCV::X5;
}
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