[llvm] 7ba4968 - [RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 18:40:56 PDT 2024
Author: Craig Topper
Date: 2024-09-12T18:40:52-07:00
New Revision: 7ba49685c020f7059fe0ba27c157ecf08b937d44
URL: https://github.com/llvm/llvm-project/commit/7ba49685c020f7059fe0ba27c157ecf08b937d44
DIFF: https://github.com/llvm/llvm-project/commit/7ba49685c020f7059fe0ba27c157ecf08b937d44.diff
LOG: [RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
llvm/test/MC/RISCV/csr-aliases.s
llvm/test/MC/RISCV/rvf-aliases-valid.s
llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa141c31f94dbd..c802274aa78c32 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -348,6 +348,11 @@ def FeatureStdExtZfinx
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
+def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
+ AssemblerPredicate<(any_of FeatureStdExtF,
+ FeatureStdExtZfinx),
+ "'F' (Single-Precision Floating-Point) or "
+ "'Zfinx' (Float in Integer)">;
def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 1442bc1cbc4feb..a00acb372dc2a2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -400,23 +400,10 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtF] in {
-def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
-def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
-
-def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-
-// fgt.s/fge.s are recognised by the GNU assembler but the canonical
-// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
-def : InstAlias<"fgt.s $rd, $rs, $rt",
- (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
-def : InstAlias<"fge.s $rd, $rs, $rt",
- (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
-
+let Predicates = [HasStdExtFOrZfinx] in {
// The following csr instructions actually alias instructions from the base ISA.
-// However, it only makes sense to support them when the F extension is enabled.
+// However, it only makes sense to support them when the F or Zfinx extension is
+// enabled.
// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
@@ -439,6 +426,22 @@ def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GP
def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
+} // Predicates = [HasStdExtFOrZfinx]
+
+let Predicates = [HasStdExtF] in {
+def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
+
+def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+
+// fgt.s/fge.s are recognised by the GNU assembler but the canonical
+// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.s $rd, $rs, $rt",
+ (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+def : InstAlias<"fge.s $rd, $rs, $rt",
+ (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
// spellings should be supported by standard tools.
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
index e864d8fb0eddd5..949668f640dbd2 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
@@ -68,18 +68,18 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ogt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: flt.d a4, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ogt:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a3, fflags
+; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: flt.d a2, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a3
+; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
@@ -119,18 +119,18 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_oge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_oge:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a3, fflags
+; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a3
+; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
@@ -172,18 +172,18 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_olt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_olt:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a3, fflags
+; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a3
+; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
@@ -223,18 +223,18 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ole:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: fle.d a4, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ole:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a3, fflags
+; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: fle.d a2, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a3
+; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
@@ -281,13 +281,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_one:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
@@ -295,13 +295,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_one:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: or a2, a4, a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -430,13 +430,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ueq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
; RV32IZFINXZDINX-NEXT: xori a4, a4, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
@@ -445,13 +445,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_ueq:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: or a3, a4, a3
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
@@ -528,9 +528,9 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ugt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: fle.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
@@ -538,9 +538,9 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_ugt:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: fle.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -582,9 +582,9 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_uge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
@@ -592,9 +592,9 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_uge:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -638,9 +638,9 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ult:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: fle.d a5, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
@@ -648,9 +648,9 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_ult:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: fle.d a3, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -692,9 +692,9 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ule:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a2, a0
-; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
@@ -702,9 +702,9 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_ule:
; RV64IZFINXZDINX: # %bb.0:
-; RV64IZFINXZDINX-NEXT: csrr a2, fflags
+; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a1, a0
-; RV64IZFINXZDINX-NEXT: csrw fflags, a2
+; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
index dae9f3e089cf4a..0cbfc96bf485ef 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
@@ -63,9 +63,9 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ogt:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a3, fflags
+; CHECKIZFINX-NEXT: frflags a3
; CHECKIZFINX-NEXT: flt.s a2, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a3
+; CHECKIZFINX-NEXT: fsflags a3
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
; CHECKIZFINX-NEXT: mv a0, a2
; CHECKIZFINX-NEXT: ret
@@ -105,9 +105,9 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_oge:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a3, fflags
+; CHECKIZFINX-NEXT: frflags a3
; CHECKIZFINX-NEXT: fle.s a2, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a3
+; CHECKIZFINX-NEXT: fsflags a3
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
; CHECKIZFINX-NEXT: mv a0, a2
; CHECKIZFINX-NEXT: ret
@@ -149,9 +149,9 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_olt:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a3, fflags
+; CHECKIZFINX-NEXT: frflags a3
; CHECKIZFINX-NEXT: flt.s a2, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a3
+; CHECKIZFINX-NEXT: fsflags a3
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
; CHECKIZFINX-NEXT: mv a0, a2
; CHECKIZFINX-NEXT: ret
@@ -191,9 +191,9 @@ define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ole:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a3, fflags
+; CHECKIZFINX-NEXT: frflags a3
; CHECKIZFINX-NEXT: fle.s a2, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a3
+; CHECKIZFINX-NEXT: fsflags a3
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
; CHECKIZFINX-NEXT: mv a0, a2
; CHECKIZFINX-NEXT: ret
@@ -240,13 +240,13 @@ define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_one:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a3, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a4, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: or a2, a4, a3
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
; CHECKIZFINX-NEXT: mv a0, a2
@@ -360,13 +360,13 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ueq:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a3, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a4, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: or a3, a4, a3
; CHECKIZFINX-NEXT: xori a2, a3, 1
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
@@ -435,9 +435,9 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ugt:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: fle.s a3, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: xori a2, a3, 1
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
; CHECKIZFINX-NEXT: mv a0, a2
@@ -479,9 +479,9 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_uge:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a3, a0, a1
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: xori a2, a3, 1
; CHECKIZFINX-NEXT: feq.s zero, a0, a1
; CHECKIZFINX-NEXT: mv a0, a2
@@ -525,9 +525,9 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ult:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: fle.s a3, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: xori a2, a3, 1
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
; CHECKIZFINX-NEXT: mv a0, a2
@@ -569,9 +569,9 @@ define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
;
; CHECKIZFINX-LABEL: fcmp_ule:
; CHECKIZFINX: # %bb.0:
-; CHECKIZFINX-NEXT: csrr a2, fflags
+; CHECKIZFINX-NEXT: frflags a2
; CHECKIZFINX-NEXT: flt.s a3, a1, a0
-; CHECKIZFINX-NEXT: csrw fflags, a2
+; CHECKIZFINX-NEXT: fsflags a2
; CHECKIZFINX-NEXT: xori a2, a3, 1
; CHECKIZFINX-NEXT: feq.s zero, a1, a0
; CHECKIZFINX-NEXT: mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
index d96c39c504e1fd..4bc595bcc4cc8f 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
@@ -61,9 +61,9 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ogt:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a3, fflags
+; CHECKIZHINX-NEXT: frflags a3
; CHECKIZHINX-NEXT: flt.h a2, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a3
+; CHECKIZHINX-NEXT: fsflags a3
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
; CHECKIZHINX-NEXT: mv a0, a2
; CHECKIZHINX-NEXT: ret
@@ -80,9 +80,9 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: csrr a3, fflags
+; CHECKIZHINXMIN-NEXT: frflags a3
; CHECKIZHINXMIN-NEXT: flt.s a0, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a3
+; CHECKIZHINXMIN-NEXT: fsflags a3
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
@@ -101,9 +101,9 @@ define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_oge:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a3, fflags
+; CHECKIZHINX-NEXT: frflags a3
; CHECKIZHINX-NEXT: fle.h a2, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a3
+; CHECKIZHINX-NEXT: fsflags a3
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
; CHECKIZHINX-NEXT: mv a0, a2
; CHECKIZHINX-NEXT: ret
@@ -120,9 +120,9 @@ define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: csrr a3, fflags
+; CHECKIZHINXMIN-NEXT: frflags a3
; CHECKIZHINXMIN-NEXT: fle.s a0, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a3
+; CHECKIZHINXMIN-NEXT: fsflags a3
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
@@ -141,9 +141,9 @@ define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_olt:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a3, fflags
+; CHECKIZHINX-NEXT: frflags a3
; CHECKIZHINX-NEXT: flt.h a2, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a3
+; CHECKIZHINX-NEXT: fsflags a3
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
; CHECKIZHINX-NEXT: mv a0, a2
; CHECKIZHINX-NEXT: ret
@@ -160,9 +160,9 @@ define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a3, fflags
+; CHECKIZHINXMIN-NEXT: frflags a3
; CHECKIZHINXMIN-NEXT: flt.s a0, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a3
+; CHECKIZHINXMIN-NEXT: fsflags a3
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
; CHECKIZHINXMIN-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
@@ -181,9 +181,9 @@ define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ole:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a3, fflags
+; CHECKIZHINX-NEXT: frflags a3
; CHECKIZHINX-NEXT: fle.h a2, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a3
+; CHECKIZHINX-NEXT: fsflags a3
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
; CHECKIZHINX-NEXT: mv a0, a2
; CHECKIZHINX-NEXT: ret
@@ -200,9 +200,9 @@ define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a3, fflags
+; CHECKIZHINXMIN-NEXT: frflags a3
; CHECKIZHINXMIN-NEXT: fle.s a0, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a3
+; CHECKIZHINXMIN-NEXT: fsflags a3
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
; CHECKIZHINXMIN-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
@@ -228,13 +228,13 @@ define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_one:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a3, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a4, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: or a2, a4, a3
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
; CHECKIZHINX-NEXT: mv a0, a2
@@ -257,13 +257,13 @@ define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a3, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a4, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: or a0, a4, a3
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
; CHECKIZHINXMIN-NEXT: ret
@@ -326,13 +326,13 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ueq:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a3, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a4, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: or a3, a4, a3
; CHECKIZHINX-NEXT: xori a2, a3, 1
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
@@ -357,13 +357,13 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a3, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a4, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: or a3, a4, a3
; CHECKIZHINXMIN-NEXT: xori a0, a3, 1
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
@@ -385,9 +385,9 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ugt:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: fle.h a3, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: xori a2, a3, 1
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
; CHECKIZHINX-NEXT: mv a0, a2
@@ -406,9 +406,9 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: fle.s a3, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: xori a0, a3, 1
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
; CHECKIZHINXMIN-NEXT: ret
@@ -429,9 +429,9 @@ define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_uge:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a3, a0, a1
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: xori a2, a3, 1
; CHECKIZHINX-NEXT: feq.h zero, a0, a1
; CHECKIZHINX-NEXT: mv a0, a2
@@ -450,9 +450,9 @@ define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a3, a2, a1
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: xori a0, a3, 1
; CHECKIZHINXMIN-NEXT: feq.s zero, a2, a1
; CHECKIZHINXMIN-NEXT: ret
@@ -473,9 +473,9 @@ define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ult:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: fle.h a3, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: xori a2, a3, 1
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
; CHECKIZHINX-NEXT: mv a0, a2
@@ -494,9 +494,9 @@ define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: fle.s a3, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: xori a0, a3, 1
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
; CHECKIZHINXMIN-NEXT: ret
@@ -517,9 +517,9 @@ define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
;
; CHECKIZHINX-LABEL: fcmp_ule:
; CHECKIZHINX: # %bb.0:
-; CHECKIZHINX-NEXT: csrr a2, fflags
+; CHECKIZHINX-NEXT: frflags a2
; CHECKIZHINX-NEXT: flt.h a3, a1, a0
-; CHECKIZHINX-NEXT: csrw fflags, a2
+; CHECKIZHINX-NEXT: fsflags a2
; CHECKIZHINX-NEXT: xori a2, a3, 1
; CHECKIZHINX-NEXT: feq.h zero, a1, a0
; CHECKIZHINX-NEXT: mv a0, a2
@@ -538,9 +538,9 @@ define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: csrr a0, fflags
+; CHECKIZHINXMIN-NEXT: frflags a0
; CHECKIZHINXMIN-NEXT: flt.s a3, a1, a2
-; CHECKIZHINXMIN-NEXT: csrw fflags, a0
+; CHECKIZHINXMIN-NEXT: fsflags a0
; CHECKIZHINXMIN-NEXT: xori a0, a3, 1
; CHECKIZHINXMIN-NEXT: feq.s zero, a1, a2
; CHECKIZHINXMIN-NEXT: ret
diff --git a/llvm/test/MC/RISCV/csr-aliases.s b/llvm/test/MC/RISCV/csr-aliases.s
index 87fce59a861124..96eb96f81bde91 100644
--- a/llvm/test/MC/RISCV/csr-aliases.s
+++ b/llvm/test/MC/RISCV/csr-aliases.s
@@ -7,6 +7,9 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
# RUN: | llvm-objdump -d --mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
# RUN: | llvm-objdump -d --mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
@@ -26,6 +29,9 @@
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
# RUN: | llvm-objdump -d --mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
# RUN: | llvm-objdump -d --mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s
index 31f931ba8a6dbd..0430e2af7c5313 100644
--- a/llvm/test/MC/RISCV/rvf-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvf-aliases-valid.s
@@ -48,7 +48,8 @@ fgt.s x4, f5, f6
fge.s x7, f8, f9
# The following instructions actually alias instructions from the base ISA.
-# However, it only makes sense to support them when the F extension is enabled.
+# However, it only makes sense to support them when the F or Zfinx extension is
+# enabled.
# CHECK-INST: csrrs t0, fcsr, zero
# CHECK-ALIAS: frcsr t0
frcsr x5
diff --git a/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s b/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
index f624c17f78a67b..f9225cf5dc2ef3 100644
--- a/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -7,16 +7,16 @@
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx \
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \
-# RUN: | llvm-objdump -d --mattr=+zfinx -M no-aliases - \
+# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx -M no-aliases - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \
-# RUN: | llvm-objdump -d --mattr=+zfinx - \
+# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx - \
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \
-# RUN: | llvm-objdump -d --mattr=+zfinx -M no-aliases - \
+# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx -M no-aliases - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \
-# RUN: | llvm-objdump -d --mattr=+zfinx - \
+# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zfinx - \
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
##===----------------------------------------------------------------------===##
@@ -40,6 +40,63 @@ fgt.s x4, s5, s6
# CHECK-ALIAS: fle.s t2, s1, s0
fge.s x7, x8, x9
+# The following instructions actually alias instructions from the base ISA.
+# However, it only makes sense to support them when the F or Zfinx extension is
+# enabled.
+# CHECK-INST: csrrs t0, fcsr, zero
+# CHECK-ALIAS: frcsr t0
+frcsr x5
+# CHECK-INST: csrrw t1, fcsr, t2
+# CHECK-ALIAS: fscsr t1, t2
+fscsr x6, x7
+# CHECK-INST: csrrw zero, fcsr, t3
+# CHECK-ALIAS: fscsr t3
+fscsr x28
+
+# These are obsolete aliases of frcsr/fscsr. They are accepted by the assembler
+# but the disassembler should always print them as the equivalent, new aliases.
+# CHECK-INST: csrrs t4, fcsr, zero
+# CHECK-ALIAS: frcsr t4
+frsr x29
+# CHECK-INST: csrrw t5, fcsr, t6
+# CHECK-ALIAS: fscsr t5, t6
+fssr x30, x31
+# CHECK-INST: csrrw zero, fcsr, s0
+# CHECK-ALIAS: fscsr s0
+fssr x8
+
+# CHECK-INST: csrrs t4, frm, zero
+# CHECK-ALIAS: frrm t4
+frrm x29
+# CHECK-INST: csrrw t5, frm, t4
+# CHECK-ALIAS: fsrm t5, t4
+fsrm x30, x29
+# CHECK-INST: csrrw zero, frm, t6
+# CHECK-ALIAS: fsrm t6
+fsrm x31
+# CHECK-INST: csrrwi a0, frm, 31
+# CHECK-ALIAS: fsrmi a0, 31
+fsrmi x10, 0x1f
+# CHECK-INST: csrrwi zero, frm, 30
+# CHECK-ALIAS: fsrmi 30
+fsrmi 0x1e
+
+# CHECK-INST: csrrs a1, fflags, zero
+# CHECK-ALIAS: frflags a1
+frflags x11
+# CHECK-INST: csrrw a2, fflags, a1
+# CHECK-ALIAS: fsflags a2, a1
+fsflags x12, x11
+# CHECK-INST: csrrw zero, fflags, a3
+# CHECK-ALIAS: fsflags a3
+fsflags x13
+# CHECK-INST: csrrwi a4, fflags, 29
+# CHECK-ALIAS: fsflagsi a4, 29
+fsflagsi x14, 0x1d
+# CHECK-INST: csrrwi zero, fflags, 28
+# CHECK-ALIAS: fsflagsi 28
+fsflagsi 0x1c
+
##===----------------------------------------------------------------------===##
## Aliases which omit the rounding mode.
##===----------------------------------------------------------------------===##
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