[llvm] [AMDGPU] Assert no bad shift operations will happen (PR #108416)

[Matt Arsenault via llvm-commits]

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@@ -4204,6 +4204,8 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
     // TODO: Should we try to emit this once in the entry block?
     const LLT S32 = LLT::scalar(32);
     const unsigned Mask = Arg->getMask();
+    // None of the target SGPRs or VGPRs are expected to have a 'zero' mask.
+    assert(Mask && "Invalid mask.");
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arsenm wrote:

Could you hide this in getMask

https://github.com/llvm/llvm-project/pull/108416