[llvm] [AMDGPU] Assert no bad shift operations will happen (PR #108416)

[Georgi Mirazchiyski via llvm-commits]

https://github.com/GeorgeWeb created https://github.com/llvm/llvm-project/pull/108416

The assumption in the asserts is based on the fact that no SGPR/VGPR register Arg mask in the ISelLowering and Legalizer can equal zero. They are implicitly set to ~0 by default (meaning non-masked) or explicitly to a non-zero value. This commit also silences static analysis tools wrt potential bad shifts.

>From 500af9f4e7f09725163ef1e5d936bacdb10b1b7a Mon Sep 17 00:00:00 2001
From: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: Thu, 12 Sep 2024 17:21:46 +0100
Subject: [PATCH] [AMDGPU] Assert no bad shift operations will happen

The assumption in the asserts is based on the fact that no SGPR/VGPR register
Arg mask in the ISelLowering and Legalizer can equal zero. They are implicitly
set to ~0 by default (meaning non-masked) or explicitly to a non-zero value.
This commit also silences static analysis tools wrt potential bad shifts.
---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp  | 2 ++
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 ++
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp         | 3 +++
 3 files changed, 7 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 8a71550e5532cd..f5035cd06cad2d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5320,6 +5320,8 @@ SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
     return V;
 
   unsigned Mask = Arg.getMask();
+  // None of the target SGPRs or VGPRs are expected to have a 'zero' mask.
+  assert(Mask && "Invalid mask.");
   unsigned Shift = llvm::countr_zero<unsigned>(Mask);
   V = DAG.getNode(ISD::SRL, SL, VT, V,
                   DAG.getShiftAmountConstant(Shift, VT, SL));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 0029c51231f286..4d0f8c40937fd8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -4204,6 +4204,8 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
     // TODO: Should we try to emit this once in the entry block?
     const LLT S32 = LLT::scalar(32);
     const unsigned Mask = Arg->getMask();
+    // None of the target SGPRs or VGPRs are expected to have a 'zero' mask.
+    assert(Mask && "Invalid mask.");
     const unsigned Shift = llvm::countr_zero<unsigned>(Mask);
 
     Register AndMaskSrc = LiveIn;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c19c3c6017a7c8..967862b49a4052 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -9769,6 +9769,9 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
     else
       return false;
 
+    // A valid Mask is required to have a single bit set, hence a non-zero and
+    // power-of-two value. This verifies that we will not do 64-bit shift below.
+    assert(llvm::has_single_bit(Mask) && "Invalid mask.");
     unsigned BitNo = llvm::countr_zero((uint64_t)Mask);
     if (IsSigned && BitNo == SrcSize - 1)
       return false;