[llvm] 1642f64 - [AArch64] Replace _Ncyc_ with _Nc_ in Neoverse scheduling models.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 06:47:18 PDT 2024
Author: David Green
Date: 2024-09-12T14:47:13+01:00
New Revision: 1642f64b525e1d73ca5a0456a187433c7f0eff4c
URL: https://github.com/llvm/llvm-project/commit/1642f64b525e1d73ca5a0456a187433c7f0eff4c
DIFF: https://github.com/llvm/llvm-project/commit/1642f64b525e1d73ca5a0456a187433c7f0eff4c.diff
LOG: [AArch64] Replace _Ncyc_ with _Nc_ in Neoverse scheduling models.
This brings them in line with the other Neoverse scheduling models, reducing
the amount of differences between them.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 4a009f84bc90b9..8a7d2af3449814 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -74,227 +74,227 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
//===----------------------------------------------------------------------===//
// Define generic 1 micro-op types
-def N2Write_1cyc_1B : SchedWriteRes<[N2UnitB]> { let Latency = 1; }
-def N2Write_1cyc_1I : SchedWriteRes<[N2UnitI]> { let Latency = 1; }
-def N2Write_1cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 1; }
-def N2Write_1cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 1; }
-def N2Write_1cyc_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }
-def N2Write_2cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 2; }
-def N2Write_3cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 3; }
-def N2Write_2cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 2;
- let ReleaseAtCycles = [2]; }
-def N2Write_3cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 3;
- let ReleaseAtCycles = [3]; }
-def N2Write_5cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 5;
- let ReleaseAtCycles = [5]; }
-def N2Write_12cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
-def N2Write_20cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
-def N2Write_4cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 4; }
-def N2Write_6cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 6; }
-def N2Write_2cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 2; }
-def N2Write_3cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 3; }
-def N2Write_4cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 4; }
-def N2Write_5cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 5; }
-def N2Write_12cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 12; }
-def N2Write_2cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 2; }
-def N2Write_3cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 3; }
-def N2Write_4cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 4; }
-def N2Write_7cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
-def N2Write_9cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 9; }
-def N2Write_10cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 10; }
-def N2Write_12cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 12; }
-def N2Write_13cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 13; }
-def N2Write_15cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 15; }
-def N2Write_16cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 16; }
-def N2Write_20cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 20; }
-def N2Write_2cyc_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 2; }
-def N2Write_3cyc_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 3; }
-def N2Write_4cyc_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 4; }
-def N2Write_6cyc_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 6; }
-def N2Write_10cyc_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 10; }
-def N2Write_6cyc_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 6; }
+def N2Write_1c_1B : SchedWriteRes<[N2UnitB]> { let Latency = 1; }
+def N2Write_1c_1I : SchedWriteRes<[N2UnitI]> { let Latency = 1; }
+def N2Write_1c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 1; }
+def N2Write_1c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 1; }
+def N2Write_1c_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }
+def N2Write_2c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 2; }
+def N2Write_3c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 3; }
+def N2Write_2c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 2;
+ let ReleaseAtCycles = [2]; }
+def N2Write_3c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 3;
+ let ReleaseAtCycles = [3]; }
+def N2Write_5c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 5;
+ let ReleaseAtCycles = [5]; }
+def N2Write_12c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 12;
+ let ReleaseAtCycles = [12]; }
+def N2Write_20c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 20;
+ let ReleaseAtCycles = [20]; }
+def N2Write_4c_1L : SchedWriteRes<[N2UnitL]> { let Latency = 4; }
+def N2Write_6c_1L : SchedWriteRes<[N2UnitL]> { let Latency = 6; }
+def N2Write_2c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 2; }
+def N2Write_3c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 3; }
+def N2Write_4c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 4; }
+def N2Write_5c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 5; }
+def N2Write_12c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 12; }
+def N2Write_2c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 2; }
+def N2Write_3c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 3; }
+def N2Write_4c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 4; }
+def N2Write_7c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 7;
+ let ReleaseAtCycles = [7]; }
+def N2Write_9c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 9; }
+def N2Write_10c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 10; }
+def N2Write_12c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 12; }
+def N2Write_13c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 13; }
+def N2Write_15c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 15; }
+def N2Write_16c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 16; }
+def N2Write_20c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 20; }
+def N2Write_2c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 2; }
+def N2Write_3c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 3; }
+def N2Write_4c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 4; }
+def N2Write_6c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 6; }
+def N2Write_10c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 10; }
+def N2Write_6c_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 6; }
//===----------------------------------------------------------------------===//
// Define generic 2 micro-op types
-def N2Write_1cyc_1B_1S : SchedWriteRes<[N2UnitB, N2UnitS]> {
+def N2Write_1c_1B_1S : SchedWriteRes<[N2UnitB, N2UnitS]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def N2Write_6cyc_1M0_1B : SchedWriteRes<[N2UnitM0, N2UnitB]> {
+def N2Write_6c_1M0_1B : SchedWriteRes<[N2UnitM0, N2UnitB]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_9cyc_1M0_1L : SchedWriteRes<[N2UnitM0, N2UnitL]> {
+def N2Write_9c_1M0_1L : SchedWriteRes<[N2UnitM0, N2UnitL]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def N2Write_3cyc_1I_1M : SchedWriteRes<[N2UnitI, N2UnitM]> {
+def N2Write_3c_1I_1M : SchedWriteRes<[N2UnitI, N2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def N2Write_4cyc_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
+def N2Write_4c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_5cyc_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
+def N2Write_5c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def N2Write_6cyc_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
+def N2Write_6c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_7cyc_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
+def N2Write_7c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def N2Write_1cyc_1L01_1D : SchedWriteRes<[N2UnitL01, N2UnitD]> {
+def N2Write_1c_1L01_1D : SchedWriteRes<[N2UnitL01, N2UnitD]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def N2Write_5cyc_1M0_1V : SchedWriteRes<[N2UnitM0, N2UnitV]> {
+def N2Write_5c_1M0_1V : SchedWriteRes<[N2UnitM0, N2UnitV]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def N2Write_2cyc_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {
+def N2Write_2c_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def N2Write_4cyc_1V1_1V : SchedWriteRes<[N2UnitV1, N2UnitV]> {
+def N2Write_4c_1V1_1V : SchedWriteRes<[N2UnitV1, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_4cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_4c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_10cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_10c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [5, 5];
}
-def N2Write_13cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_13c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 13;
let NumMicroOps = 2;
let ReleaseAtCycles = [6, 7];
}
-def N2Write_15cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_15c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 15;
let NumMicroOps = 2;
let ReleaseAtCycles = [7, 8];
}
-def N2Write_16cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_16c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 16;
let NumMicroOps = 2;
let ReleaseAtCycles = [8, 8];
}
-def N2Write_4cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
+def N2Write_4c_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_6cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
+def N2Write_6c_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_6cyc_2L : SchedWriteRes<[N2UnitL, N2UnitL]> {
+def N2Write_6c_2L : SchedWriteRes<[N2UnitL, N2UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_8cyc_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {
+def N2Write_8c_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def N2Write_4cyc_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {
+def N2Write_4c_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_3cyc_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {
+def N2Write_3c_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def N2Write_2cyc_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {
+def N2Write_2c_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def N2Write_6cyc_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {
+def N2Write_6c_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_4cyc_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {
+def N2Write_4c_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def N2Write_5cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
+def N2Write_5c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def N2Write_5cyc_1V1_1M0 : SchedWriteRes<[N2UnitV1, N2UnitM0]> {
+def N2Write_5c_1V1_1M0 : SchedWriteRes<[N2UnitV1, N2UnitM0]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def N2Write_7cyc_1M0_1V0 : SchedWriteRes<[N2UnitM0, N2UnitV0]> {
+def N2Write_7c_1M0_1V0 : SchedWriteRes<[N2UnitM0, N2UnitV0]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def N2Write_2cyc_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {
+def N2Write_2c_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def N2Write_6cyc_1V_1V1 : SchedWriteRes<[N2UnitV, N2UnitV1]> {
+def N2Write_6c_1V_1V1 : SchedWriteRes<[N2UnitV, N2UnitV1]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_6cyc_1L_1M : SchedWriteRes<[N2UnitL, N2UnitM]> {
+def N2Write_6c_1L_1M : SchedWriteRes<[N2UnitL, N2UnitM]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_6cyc_1L_1S : SchedWriteRes<[N2UnitL, N2UnitS]> {
+def N2Write_6c_1L_1S : SchedWriteRes<[N2UnitL, N2UnitS]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def N2Write_9cyc_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {
+def N2Write_9c_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def N2Write_4cyc_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {
+def N2Write_4c_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {
let Latency = 4;
let NumMicroOps = 2;
}
@@ -302,52 +302,52 @@ def N2Write_4cyc_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {
//===----------------------------------------------------------------------===//
// Define generic 3 micro-op types
-def N2Write_1cyc_1L01_1D_1I : SchedWriteRes<[N2UnitL01, N2UnitD, N2UnitI]> {
+def N2Write_1c_1L01_1D_1I : SchedWriteRes<[N2UnitL01, N2UnitD, N2UnitI]> {
let Latency = 1;
let NumMicroOps = 3;
}
-def N2Write_2cyc_1L01_1V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitI]> {
+def N2Write_2c_1L01_1V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitI]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def N2Write_2cyc_1L01_2V : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV]> {
+def N2Write_2c_1L01_2V : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def N2Write_7cyc_1M_1M0_1V : SchedWriteRes<[N2UnitM, N2UnitM0, N2UnitV]> {
+def N2Write_7c_1M_1M0_1V : SchedWriteRes<[N2UnitM, N2UnitM0, N2UnitV]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def N2Write_8cyc_1M0_1V1_1V : SchedWriteRes<[N2UnitM0, N2UnitV1, N2UnitV]> {
+def N2Write_8c_1M0_1V1_1V : SchedWriteRes<[N2UnitM0, N2UnitV1, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 3;
}
-def N2Write_10cyc_1V_1L_1S : SchedWriteRes<[N2UnitV, N2UnitL, N2UnitL]> {
+def N2Write_10c_1V_1L_1S : SchedWriteRes<[N2UnitV, N2UnitL, N2UnitL]> {
let Latency = 10;
let NumMicroOps = 3;
}
-def N2Write_2cyc_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {
+def N2Write_2c_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def N2Write_4cyc_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {
+def N2Write_4c_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 3;
}
-def N2Write_6cyc_3L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL]> {
+def N2Write_6c_3L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL]> {
let Latency = 6;
let NumMicroOps = 3;
}
-def N2Write_8cyc_1L_2V : SchedWriteRes<[N2UnitL, N2UnitV, N2UnitV]> {
+def N2Write_8c_1L_2V : SchedWriteRes<[N2UnitL, N2UnitV, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 3;
}
@@ -355,102 +355,102 @@ def N2Write_8cyc_1L_2V : SchedWriteRes<[N2UnitL, N2UnitV, N2UnitV]> {
//===----------------------------------------------------------------------===//
// Define generic 4 micro-op types
-def N2Write_2cyc_1L01_2V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,
- N2UnitI]> {
+def N2Write_2c_1L01_2V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,
+ N2UnitI]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def N2Write_6cyc_4V0 : SchedWriteRes<[N2UnitV0, N2UnitV0, N2UnitV0, N2UnitV0]> {
+def N2Write_6c_4V0 : SchedWriteRes<[N2UnitV0, N2UnitV0, N2UnitV0, N2UnitV0]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def N2Write_4cyc_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_4c_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def N2Write_6cyc_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_6c_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def N2Write_8cyc_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
+def N2Write_8c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def N2Write_9cyc_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
+def N2Write_9c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
let Latency = 9;
let NumMicroOps = 4;
}
-def N2Write_2cyc_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
- N2UnitV]> {
+def N2Write_2c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
+ N2UnitV]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def N2Write_4cyc_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
- N2UnitV]> {
+def N2Write_4c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
+ N2UnitV]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def N2Write_5cyc_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
- N2UnitV]> {
+def N2Write_5c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,
+ N2UnitV]> {
let Latency = 5;
let NumMicroOps = 4;
}
-def N2Write_8cyc_2M0_2V0 : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitV0,
- N2UnitV0]> {
+def N2Write_8c_2M0_2V0 : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitV0,
+ N2UnitV0]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def N2Write_11cyc_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
- N2UnitV1]> {
+def N2Write_11c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
+ N2UnitV1]> {
let Latency = 11;
let NumMicroOps = 4;
}
-def N2Write_9cyc_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
- N2UnitV1]> {
+def N2Write_9c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
+ N2UnitV1]> {
let Latency = 9;
let NumMicroOps = 4;
}
-def N2Write_8cyc_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
- N2UnitV1]> {
+def N2Write_8c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
+ N2UnitV1]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def N2Write_10cyc_2L_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
- N2UnitV1]> {
+def N2Write_10c_2L_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,
+ N2UnitV1]> {
let Latency = 10;
let NumMicroOps = 4;
}
-def N2Write_10cyc_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
+def N2Write_10c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {
let Latency = 10;
let NumMicroOps = 4;
}
-def N2Write_4cyc_2M0_2M : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitM,
- N2UnitM]> {
+def N2Write_4c_2M0_2M : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitM,
+ N2UnitM]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def N2Write_6cyc_2I_2L : SchedWriteRes<[N2UnitI, N2UnitI, N2UnitL, N2UnitL]> {
+def N2Write_6c_2I_2L : SchedWriteRes<[N2UnitI, N2UnitI, N2UnitL, N2UnitL]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def N2Write_7cyc_4L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL]> {
+def N2Write_7c_4L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL]> {
let Latency = 7;
let NumMicroOps = 4;
}
@@ -458,14 +458,14 @@ def N2Write_7cyc_4L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL]> {
//===----------------------------------------------------------------------===//
// Define generic 5 micro-op types
-def N2Write_2cyc_1L01_2V_2I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,
- N2UnitI, N2UnitI]> {
+def N2Write_2c_1L01_2V_2I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,
+ N2UnitI, N2UnitI]> {
let Latency = 2;
let NumMicroOps = 5;
}
-def N2Write_8cyc_2L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
- N2UnitV]> {
+def N2Write_8c_2L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
+ N2UnitV]> {
let Latency = 8;
let NumMicroOps = 5;
}
@@ -473,32 +473,32 @@ def N2Write_8cyc_2L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
//===----------------------------------------------------------------------===//
// Define generic 6 micro-op types
-def N2Write_8cyc_3L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_8c_3L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 6;
}
-def N2Write_2cyc_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_2c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 2;
let NumMicroOps = 6;
}
-def N2Write_6cyc_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_6c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 6;
let NumMicroOps = 6;
}
-def N2Write_4cyc_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_4c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 4;
let NumMicroOps = 6;
}
-def N2Write_10cyc_2L_2V_2S : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
- N2UnitS, N2UnitS]> {
+def N2Write_10c_2L_2V_2S : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
+ N2UnitS, N2UnitS]> {
let Latency = 10;
let NumMicroOps = 6;
}
@@ -506,8 +506,8 @@ def N2Write_10cyc_2L_2V_2S : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,
//===----------------------------------------------------------------------===//
// Define generic 7 micro-op types
-def N2Write_8cyc_3L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_8c_3L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 7;
}
@@ -515,34 +515,34 @@ def N2Write_8cyc_3L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 8 micro-op types
-def N2Write_6cyc_8V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_6c_8V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 6;
let NumMicroOps = 8;
}
-def N2Write_2cyc_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitV, N2UnitV, N2UnitV,
- N2UnitV]> {
+def N2Write_2c_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV]> {
let Latency = 2;
let NumMicroOps = 8;
}
-def N2Write_5cyc_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitV, N2UnitV, N2UnitV,
- N2UnitV]> {
+def N2Write_5c_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV]> {
let Latency = 5;
let NumMicroOps = 8;
}
-def N2Write_8cyc_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_8c_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 8;
let NumMicroOps = 8;
}
-def N2Write_9cyc_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_9c_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 9;
let NumMicroOps = 8;
}
@@ -550,9 +550,9 @@ def N2Write_9cyc_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 10 micro-op types
-def N2Write_7cyc_5L01_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_7c_5L01_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 7;
let NumMicroOps = 10;
}
@@ -560,10 +560,10 @@ def N2Write_7cyc_5L01_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 12 micro-op types
-def N2Write_7cyc_6L01_6V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitV, N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV]> {
+def N2Write_7c_6L01_6V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitV, N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV]> {
let Latency = 7;
let NumMicroOps = 12;
}
@@ -571,11 +571,11 @@ def N2Write_7cyc_6L01_6V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 15 micro-op types
-def N2Write_7cyc_5L01_5S_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitS,
- N2UnitS, N2UnitS, N2UnitS,
- N2UnitS, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_7c_5L01_5S_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitS,
+ N2UnitS, N2UnitS, N2UnitS,
+ N2UnitS, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 7;
let NumMicroOps = 15;
}
@@ -583,12 +583,12 @@ def N2Write_7cyc_5L01_5S_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 18 micro-op types
-def N2Write_11cyc_9L01_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_11c_9L01_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 11;
let NumMicroOps = 18;
}
@@ -596,15 +596,15 @@ def N2Write_11cyc_9L01_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 27 micro-op types
-def N2Write_11cyc_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitL01, N2UnitL01, N2UnitL01,
- N2UnitS, N2UnitS, N2UnitS,
- N2UnitS, N2UnitS, N2UnitS,
- N2UnitS, N2UnitS, N2UnitS,
- N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV,
- N2UnitV, N2UnitV, N2UnitV]> {
+def N2Write_11c_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitL01, N2UnitL01, N2UnitL01,
+ N2UnitS, N2UnitS, N2UnitS,
+ N2UnitS, N2UnitS, N2UnitS,
+ N2UnitS, N2UnitS, N2UnitS,
+ N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV,
+ N2UnitV, N2UnitV, N2UnitV]> {
let Latency = 11;
let NumMicroOps = 27;
}
@@ -612,12 +612,12 @@ def N2Write_11cyc_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
//===----------------------------------------------------------------------===//
// Define types for arithmetic and logical ops with short shifts
def N2Write_Arith : SchedWriteVariant<[
- SchedVar<IsCheapLSL, [N2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [N2Write_1c_1I]>,
+ SchedVar<NoSchedPred, [N2Write_2c_1M]>]>;
def N2Write_Logical: SchedWriteVariant<[
- SchedVar<NeoverseNoLSL, [N2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
+ SchedVar<NeoverseNoLSL, [N2Write_1c_1I]>,
+ SchedVar<NoSchedPred, [N2Write_2c_1M]>]>;
// Miscellaneous
// -----------------------------------------------------------------------------
@@ -629,24 +629,24 @@ def : InstRW<[WriteI], (instrs COPY)>;
// Branch, immed
// Compare and branch
-def : SchedAlias<WriteBr, N2Write_1cyc_1B>;
+def : SchedAlias<WriteBr, N2Write_1c_1B>;
// Branch, register
-def : SchedAlias<WriteBrReg, N2Write_1cyc_1B>;
+def : SchedAlias<WriteBrReg, N2Write_1c_1B>;
// Branch and link, immed
// Branch and link, register
-def : InstRW<[N2Write_1cyc_1B_1S], (instrs BL, BLR)>;
+def : InstRW<[N2Write_1c_1B_1S], (instrs BL, BLR)>;
// Arithmetic and Logical Instructions
// -----------------------------------------------------------------------------
// ALU, basic
// ALU, basic, flagset
-def : SchedAlias<WriteI, N2Write_1cyc_1I>;
+def : SchedAlias<WriteI, N2Write_1c_1I>;
// ALU, extend and shift
-def : SchedAlias<WriteIEReg, N2Write_2cyc_1M>;
+def : SchedAlias<WriteIEReg, N2Write_2c_1M>;
// Arithmetic, LSL shift, shift <= 4
// Arithmetic, flagset, LSL shift, shift <= 4
@@ -654,44 +654,44 @@ def : SchedAlias<WriteIEReg, N2Write_2cyc_1M>;
def : SchedAlias<WriteISReg, N2Write_Arith>;
// Logical, shift, no flagset
-def : InstRW<[N2Write_1cyc_1I],
+def : InstRW<[N2Write_1c_1I],
(instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
// Logical, shift, flagset
def : InstRW<[N2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
// Arithmetic, immediate to logical address tag
-def : InstRW<[N2Write_2cyc_1M], (instrs ADDG, SUBG)>;
+def : InstRW<[N2Write_2c_1M], (instrs ADDG, SUBG)>;
// Convert floating-point condition flags
// Flag manipulation instructions
def : WriteRes<WriteSys, []> { let Latency = 1; }
// Insert Random Tags
-def : InstRW<[N2Write_2cyc_1M], (instrs IRG, IRGstack)>;
+def : InstRW<[N2Write_2c_1M], (instrs IRG, IRGstack)>;
// Insert Tag Mask
// Subtract Pointer
// Subtract Pointer, flagset
-def : InstRW<[N2Write_1cyc_1I], (instrs GMI, SUBP, SUBPS)>;
+def : InstRW<[N2Write_1c_1I], (instrs GMI, SUBP, SUBPS)>;
// Move and shift instructions
// -----------------------------------------------------------------------------
-def : SchedAlias<WriteImm, N2Write_1cyc_1I>;
+def : SchedAlias<WriteImm, N2Write_1c_1I>;
// Divide and Multiply Instructions
// -----------------------------------------------------------------------------
// SDIV, UDIV
-def : SchedAlias<WriteID32, N2Write_12cyc_1M0>;
-def : SchedAlias<WriteID64, N2Write_20cyc_1M0>;
+def : SchedAlias<WriteID32, N2Write_12c_1M0>;
+def : SchedAlias<WriteID64, N2Write_20c_1M0>;
def : WriteRes<WriteIM32, [N2UnitM]> { let Latency = 2; }
def : WriteRes<WriteIM64, [N2UnitM]> { let Latency = 2; }
// Multiply high
-def : InstRW<[N2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>;
+def : InstRW<[N2Write_3c_1M], (instrs SMULHrr, UMULHrr)>;
// Pointer Authentication Instructions (v8.3 PAC)
// -----------------------------------------------------------------------------
@@ -701,21 +701,21 @@ def : InstRW<[N2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>;
// Compute pointer authentication code for data address
// Compute pointer authentication code, using generic key
// Compute pointer authentication code for instruction address
-def : InstRW<[N2Write_5cyc_1M0], (instregex "^AUT", "^PAC")>;
+def : InstRW<[N2Write_5c_1M0], (instregex "^AUT", "^PAC")>;
// Branch and link, register, with pointer authentication
// Branch, register, with pointer authentication
// Branch, return, with pointer authentication
-def : InstRW<[N2Write_6cyc_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,
- BRAAZ, BRAB, BRABZ, RETAA, RETAB,
- ERETAA, ERETAB)>;
+def : InstRW<[N2Write_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,
+ BRAAZ, BRAB, BRABZ, RETAA, RETAB,
+ ERETAA, ERETAB)>;
// Load register, with pointer authentication
-def : InstRW<[N2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
+def : InstRW<[N2Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
// Strip pointer authentication code
-def : InstRW<[N2Write_2cyc_1M0], (instrs XPACD, XPACI, XPACLRI)>;
+def : InstRW<[N2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
// Miscellaneous data-processing instructions
// -----------------------------------------------------------------------------
@@ -724,41 +724,41 @@ def : InstRW<[N2Write_2cyc_1M0], (instrs XPACD, XPACI, XPACLRI)>;
// Bitfield extract, two regs
// NOTE: We don't model the
diff erence between EXTR where both operands are the
// same (one reg).
-def : SchedAlias<WriteExtr, N2Write_3cyc_1I_1M>;
-def : InstRW<[N2Write_3cyc_1I_1M], (instrs EXTRWrri, EXTRXrri)>;
+def : SchedAlias<WriteExtr, N2Write_3c_1I_1M>;
+def : InstRW<[N2Write_3c_1I_1M], (instrs EXTRWrri, EXTRXrri)>;
// Bitfield move, basic
-def : SchedAlias<WriteIS, N2Write_1cyc_1I>;
+def : SchedAlias<WriteIS, N2Write_1c_1I>;
// Bitfield move, insert
-def : InstRW<[N2Write_2cyc_1M], (instregex "^BFM[WX]ri$")>;
+def : InstRW<[N2Write_2c_1M], (instregex "^BFM[WX]ri$")>;
// Load instructions
// -----------------------------------------------------------------------------
-def : SchedAlias<WriteLD, N2Write_4cyc_1L>;
-def : SchedAlias<WriteLDIdx, N2Write_4cyc_1I_1L>;
+def : SchedAlias<WriteLD, N2Write_4c_1L>;
+def : SchedAlias<WriteLDIdx, N2Write_4c_1I_1L>;
// Load pair, signed immed offset, signed words
-def : InstRW<[N2Write_5cyc_1M0, WriteLDHi], (instrs LDPSWi)>;
+def : InstRW<[N2Write_5c_1M0, WriteLDHi], (instrs LDPSWi)>;
// Load pair, immed post-index or immed pre-index, signed words
-def : InstRW<[WriteAdr, N2Write_5cyc_1M0, WriteLDHi],
+def : InstRW<[WriteAdr, N2Write_5c_1M0, WriteLDHi],
(instregex "^LDPSW(post|pre)$")>;
// Store instructions
// -----------------------------------------------------------------------------
-def : SchedAlias<WriteST, N2Write_1cyc_1L01_1D>;
-def : SchedAlias<WriteSTIdx, N2Write_1cyc_1L01_1D_1I>;
-def : SchedAlias<WriteSTP, N2Write_1cyc_1L01_1D>;
-def : SchedAlias<WriteAdr, N2Write_1cyc_1I>; // copied from A57.
+def : SchedAlias<WriteST, N2Write_1c_1L01_1D>;
+def : SchedAlias<WriteSTIdx, N2Write_1c_1L01_1D_1I>;
+def : SchedAlias<WriteSTP, N2Write_1c_1L01_1D>;
+def : SchedAlias<WriteAdr, N2Write_1c_1I>; // copied from A57.
// Tag load instructions
// -----------------------------------------------------------------------------
// Load allocation tag
// Load multiple allocation tags
-def : InstRW<[N2Write_4cyc_1L], (instrs LDG, LDGM)>;
+def : InstRW<[N2Write_4c_1L], (instrs LDG, LDGM)>;
// Tag store instructions
// -----------------------------------------------------------------------------
@@ -769,18 +769,18 @@ def : InstRW<[N2Write_4cyc_1L], (instrs LDG, LDGM)>;
// Store Allocation Tag to one or two granules, zeroing, pre-index
// Store allocation tag and reg pair to memory, post-Index
// Store allocation tag and reg pair to memory, pre-Index
-def : InstRW<[N2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
- ST2GPreIndex, ST2GPostIndex,
- STZGPreIndex, STZGPostIndex,
- STZ2GPreIndex, STZ2GPostIndex,
- STGPpre, STGPpost)>;
+def : InstRW<[N2Write_1c_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
+ ST2GPreIndex, ST2GPostIndex,
+ STZGPreIndex, STZGPostIndex,
+ STZ2GPreIndex, STZ2GPostIndex,
+ STGPpre, STGPpost)>;
// Store allocation tags to one or two granules, signed offset
// Store allocation tag to two granules, zeroing, signed offset
// Store allocation tag and reg pair to memory, signed offset
// Store multiple allocation tags
-def : InstRW<[N2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi,
- STZ2Gi, STGPi, STGM, STZGM)>;
+def : InstRW<[N2Write_1c_1L01_1D], (instrs STGi, ST2Gi, STZGi,
+ STZ2Gi, STGPi, STGM, STZGM)>;
// FP data processing instructions
// -----------------------------------------------------------------------------
@@ -790,124 +790,124 @@ def : InstRW<[N2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi,
// FP min/max
// FP negate
// FP select
-def : SchedAlias<WriteF, N2Write_2cyc_1V>;
+def : SchedAlias<WriteF, N2Write_2c_1V>;
// FP compare
-def : SchedAlias<WriteFCmp, N2Write_2cyc_1V0>;
+def : SchedAlias<WriteFCmp, N2Write_2c_1V0>;
// FP divide, square root
-def : SchedAlias<WriteFDiv, N2Write_7cyc_1V0>;
+def : SchedAlias<WriteFDiv, N2Write_7c_1V0>;
// FP divide, H-form
-def : InstRW<[N2Write_7cyc_1V0], (instrs FDIVHrr)>;
+def : InstRW<[N2Write_7c_1V0], (instrs FDIVHrr)>;
// FP divide, S-form
-def : InstRW<[N2Write_10cyc_1V0], (instrs FDIVSrr)>;
+def : InstRW<[N2Write_10c_1V0], (instrs FDIVSrr)>;
// FP divide, D-form
-def : InstRW<[N2Write_15cyc_1V0], (instrs FDIVDrr)>;
+def : InstRW<[N2Write_15c_1V0], (instrs FDIVDrr)>;
// FP square root, H-form
-def : InstRW<[N2Write_7cyc_1V0], (instrs FSQRTHr)>;
+def : InstRW<[N2Write_7c_1V0], (instrs FSQRTHr)>;
// FP square root, S-form
-def : InstRW<[N2Write_9cyc_1V0], (instrs FSQRTSr)>;
+def : InstRW<[N2Write_9c_1V0], (instrs FSQRTSr)>;
// FP square root, D-form
-def : InstRW<[N2Write_16cyc_1V0], (instrs FSQRTDr)>;
+def : InstRW<[N2Write_16c_1V0], (instrs FSQRTDr)>;
// FP multiply
def : WriteRes<WriteFMul, [N2UnitV]> { let Latency = 3; }
// FP multiply accumulate
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
// FP round to integral
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",
- "^FRINT(32|64)[XZ][SD]r$")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",
+ "^FRINT(32|64)[XZ][SD]r$")>;
// FP miscellaneous instructions
// -----------------------------------------------------------------------------
// FP convert, from gen to vec reg
-def : InstRW<[N2Write_3cyc_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
+def : InstRW<[N2Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
// FP convert, from vec to gen reg
-def : InstRW<[N2Write_3cyc_1V], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
// FP convert, Javascript from vec to gen reg
// FP convert, from vec to vec reg
-def : SchedAlias<WriteFCvt, N2Write_3cyc_1V0>;
+def : SchedAlias<WriteFCvt, N2Write_3c_1V0>;
// FP move, immed
// FP move, register
-def : SchedAlias<WriteFImm, N2Write_2cyc_1V>;
+def : SchedAlias<WriteFImm, N2Write_2c_1V>;
// FP transfer, from gen to low half of vec reg
-def : InstRW<[N2Write_3cyc_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
- FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>;
+def : InstRW<[N2Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
+ FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>;
// FP transfer, from gen to high half of vec reg
-def : InstRW<[N2Write_5cyc_1M0_1V], (instrs FMOVXDHighr)>;
+def : InstRW<[N2Write_5c_1M0_1V], (instrs FMOVXDHighr)>;
// FP transfer, from vec to gen reg
-def : SchedAlias<WriteFCopy, N2Write_2cyc_1V>;
+def : SchedAlias<WriteFCopy, N2Write_2c_1V>;
// FP load instructions
// -----------------------------------------------------------------------------
// Load vector reg, literal, S/D/Q forms
// Load vector reg, unscaled immed
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[SDQ]l$",
- "^LDUR[BHSDQ]i$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LDR[SDQ]l$",
+ "^LDUR[BHSDQ]i$")>;
// Load vector reg, immed post-index
-def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
+def : InstRW<[N2Write_6c_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
// Load vector reg, immed pre-index
-def : InstRW<[WriteAdr, N2Write_6cyc_1I_1L], (instregex "^LDR[BHSDQ]pre$")>;
+def : InstRW<[WriteAdr, N2Write_6c_1I_1L], (instregex "^LDR[BHSDQ]pre$")>;
// Load vector reg, unsigned immed
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;
// Load vector reg, register offset, basic
// Load vector reg, register offset, scale, S/D-form
// Load vector reg, register offset, extend
// Load vector reg, register offset, extend, scale, S/D-form
-def : InstRW<[N2Write_6cyc_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
+def : InstRW<[N2Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
// Load vector reg, register offset, scale, H/Q-form
// Load vector reg, register offset, extend, scale, H/Q-form
-def : InstRW<[N2Write_7cyc_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
+def : InstRW<[N2Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
// Load vector pair, immed offset, S/D-form
-def : InstRW<[N2Write_6cyc_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;
+def : InstRW<[N2Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;
// Load vector pair, immed offset, Q-form
-def : InstRW<[N2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
+def : InstRW<[N2Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
// Load vector pair, immed post-index, S/D-form
// Load vector pair, immed pre-index, S/D-form
-def : InstRW<[WriteAdr, N2Write_6cyc_1I_1L, WriteLDHi],
+def : InstRW<[WriteAdr, N2Write_6c_1I_1L, WriteLDHi],
(instregex "^LDP[SD](pre|post)$")>;
// Load vector pair, immed post-index, Q-form
// Load vector pair, immed pre-index, Q-form
-def : InstRW<[WriteAdr, N2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
- LDPQpre)>;
+def : InstRW<[WriteAdr, N2Write_6c_2I_2L, WriteLDHi], (instrs LDPQpost,
+ LDPQpre)>;
// FP store instructions
// -----------------------------------------------------------------------------
// Store vector reg, unscaled immed, B/H/S/D-form
// Store vector reg, unscaled immed, Q-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STUR[BHSDQ]i$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STUR[BHSDQ]i$")>;
// Store vector reg, immed post-index, B/H/S/D-form
// Store vector reg, immed post-index, Q-form
// Store vector reg, immed pre-index, B/H/S/D-form
// Store vector reg, immed pre-index, Q-form
-def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V_1I, ReadAdrBase],
+def : InstRW<[WriteAdr, N2Write_2c_1L01_1V_1I, ReadAdrBase],
(instregex "^STR[BHSDQ](pre|post)$")>;
// Store vector reg, unsigned immed, B/H/S/D-form
// Store vector reg, unsigned immed, Q-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STR[BHSDQ]ui$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STR[BHSDQ]ui$")>;
// Store vector reg, register offset, basic, B/H/S/D-form
// Store vector reg, register offset, basic, Q-form
@@ -915,35 +915,35 @@ def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STR[BHSDQ]ui$")>;
// Store vector reg, register offset, extend, B/H/S/D-form
// Store vector reg, register offset, extend, Q-form
// Store vector reg, register offset, extend, scale, S/D-form
-def : InstRW<[N2Write_2cyc_1L01_1V, ReadAdrBase],
+def : InstRW<[N2Write_2c_1L01_1V, ReadAdrBase],
(instregex "^STR[BSD]ro[WX]$")>;
// Store vector reg, register offset, scale, H-form
// Store vector reg, register offset, scale, Q-form
// Store vector reg, register offset, extend, scale, H-form
// Store vector reg, register offset, extend, scale, Q-form
-def : InstRW<[N2Write_2cyc_1L01_1V, ReadAdrBase],
+def : InstRW<[N2Write_2c_1L01_1V, ReadAdrBase],
(instregex "^STR[HQ]ro[WX]$")>;
// Store vector pair, immed offset, S-form
// Store vector pair, immed offset, D-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STN?P[SD]i$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STN?P[SD]i$")>;
// Store vector pair, immed offset, Q-form
-def : InstRW<[N2Write_2cyc_1L01_2V], (instrs STPQi, STNPQi)>;
+def : InstRW<[N2Write_2c_1L01_2V], (instrs STPQi, STNPQi)>;
// Store vector pair, immed post-index, S-form
// Store vector pair, immed post-index, D-form
// Store vector pair, immed pre-index, S-form
// Store vector pair, immed pre-index, D-form
-def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V_1I],
+def : InstRW<[WriteAdr, N2Write_2c_1L01_1V_1I],
(instregex "^STP[SD](pre|post)$")>;
// Store vector pair, immed post-index, Q-form
-def : InstRW<[N2Write_2cyc_1L01_2V_1I], (instrs STPQpost)>;
+def : InstRW<[N2Write_2c_1L01_2V_1I], (instrs STPQpost)>;
// Store vector pair, immed pre-index, Q-form
-def : InstRW<[N2Write_2cyc_1L01_2V_2I], (instrs STPQpre)>;
+def : InstRW<[N2Write_2c_1L01_2V_2I], (instrs STPQpre)>;
// ASIMD integer instructions
// -----------------------------------------------------------------------------
@@ -956,82 +956,82 @@ def : InstRW<[N2Write_2cyc_1L01_2V_2I], (instrs STPQpre)>;
// ASIMD compare
// ASIMD logical
// ASIMD max/min, basic and pair-wise
-def : SchedAlias<WriteVd, N2Write_2cyc_1V>;
-def : SchedAlias<WriteVq, N2Write_2cyc_1V>;
+def : SchedAlias<WriteVd, N2Write_2c_1V>;
+def : SchedAlias<WriteVq, N2Write_2c_1V>;
// ASIMD absolute
diff accum
// ASIMD absolute
diff accum long
-def : InstRW<[N2Write_4cyc_1V1],
+def : InstRW<[N2Write_4c_1V1],
(instregex "^SABAv", "^UABAv", "^SABALv", "^UABALv")>;
// ASIMD arith, reduce, 4H/4S
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;
// ASIMD arith, reduce, 8B/8H
-def : InstRW<[N2Write_4cyc_1V1_1V],
+def : InstRW<[N2Write_4c_1V1_1V],
(instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;
// ASIMD arith, reduce, 16B
-def : InstRW<[N2Write_4cyc_1V1], (instrs ADDVv16i8v, SADDLVv16i8v,
- UADDLVv16i8v)>;
+def : InstRW<[N2Write_4c_1V1], (instrs ADDVv16i8v, SADDLVv16i8v,
+ UADDLVv16i8v)>;
// ASIMD dot product
// ASIMD dot product using signed and unsigned integers
-def : InstRW<[N2Write_3cyc_1V],
+def : InstRW<[N2Write_3c_1V],
(instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;
// ASIMD matrix multiply-accumulate
-def : InstRW<[N2Write_3cyc_1V], (instrs SMMLA, UMMLA, USMMLA)>;
+def : InstRW<[N2Write_3c_1V], (instrs SMMLA, UMMLA, USMMLA)>;
// ASIMD max/min, reduce, 4H/4S
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^[SU](MAX|MIN)Vv4i16v$",
- "^[SU](MAX|MIN)Vv4i32v$")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^[SU](MAX|MIN)Vv4i16v$",
+ "^[SU](MAX|MIN)Vv4i32v$")>;
// ASIMD max/min, reduce, 8B/8H
-def : InstRW<[N2Write_4cyc_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",
- "^[SU](MAX|MIN)Vv8i16v$")>;
+def : InstRW<[N2Write_4c_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",
+ "^[SU](MAX|MIN)Vv8i16v$")>;
// ASIMD max/min, reduce, 16B
-def : InstRW<[N2Write_4cyc_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;
+def : InstRW<[N2Write_4c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;
// ASIMD multiply
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;
// ASIMD multiply accumulate
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^MLAv", "^MLSv")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^MLAv", "^MLSv")>;
// ASIMD multiply accumulate high
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
// ASIMD multiply accumulate long
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;
// ASIMD multiply accumulate saturating long
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQDMLALv", "^SQDMLSLv")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMLALv", "^SQDMLSLv")>;
// ASIMD multiply/multiply long (8x8) polynomial, D-form
// ASIMD multiply/multiply long (8x8) polynomial, Q-form
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;
// ASIMD multiply long
-def : InstRW<[N2Write_3cyc_1V], (instregex "^[SU]MULLv", "^SQDMULLv")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^[SU]MULLv", "^SQDMULLv")>;
// ASIMD pairwise add and accumulate long
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]ADALPv")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ADALPv")>;
// ASIMD shift accumulate
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]SRAv", "^[SU]RSRAv")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]SRAv", "^[SU]RSRAv")>;
// ASIMD shift by immed, basic
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^SHLv", "^SHLLv", "^SHRNv",
- "^SSHLLv", "^SSHRv", "^USHLLv",
- "^USHRv")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^SHLv", "^SHLLv", "^SHRNv",
+ "^SSHLLv", "^SSHRv", "^USHLLv",
+ "^USHRv")>;
// ASIMD shift by immed and insert, basic
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^SLIv", "^SRIv")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^SLIv", "^SRIv")>;
// ASIMD shift by immed, complex
-def : InstRW<[N2Write_4cyc_1V1],
+def : InstRW<[N2Write_4c_1V1],
(instregex "^RSHRNv", "^SQRSHRNv", "^SQRSHRUNv",
"^(SQSHLU?|UQSHL)[bhsd]$",
"^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",
@@ -1039,10 +1039,10 @@ def : InstRW<[N2Write_4cyc_1V1],
"^UQSHRNv", "^URSHRv")>;
// ASIMD shift by register, basic
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^[SU]SHLv")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^[SU]SHLv")>;
// ASIMD shift by register, complex
-def : InstRW<[N2Write_4cyc_1V1],
+def : InstRW<[N2Write_4c_1V1],
(instregex "^[SU]RSHLv", "^[SU]QRSHLv",
"^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;
@@ -1059,110 +1059,110 @@ def : InstRW<[N2Write_4cyc_1V1],
// Handled by SchedAlias<WriteV[dq], ...>
// ASIMD FP complex multiply add
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FCMLAv")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FCMLAv")>;
// ASIMD FP convert, long (F16 to F32)
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FCVTL(v4|v8)i16")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTL(v4|v8)i16")>;
// ASIMD FP convert, long (F32 to F64)
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FCVTL(v2|v4)i32")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FCVTL(v2|v4)i32")>;
// ASIMD FP convert, narrow (F32 to F16)
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FCVTN(v4|v8)i16")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTN(v4|v8)i16")>;
// ASIMD FP convert, narrow (F64 to F32)
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FCVTN(v2|v4)i32",
- "^FCVTXN(v2|v4)f32")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32",
+ "^FCVTXN(v2|v4)f32")>;
// ASIMD FP convert, other, D-form F32 and Q-form F64
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",
- "^[SU]CVTFv2f(32|64)$")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",
+ "^[SU]CVTFv2f(32|64)$")>;
// ASIMD FP convert, other, D-form F16 and Q-form F32
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",
- "^[SU]CVTFv4f(16|32)$")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",
+ "^[SU]CVTFv4f(16|32)$")>;
// ASIMD FP convert, other, Q-form F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",
- "^[SU]CVTFv8f16$")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",
+ "^[SU]CVTFv8f16$")>;
// ASIMD FP divide, D-form, F16
-def : InstRW<[N2Write_7cyc_1V0], (instrs FDIVv4f16)>;
+def : InstRW<[N2Write_7c_1V0], (instrs FDIVv4f16)>;
// ASIMD FP divide, D-form, F32
-def : InstRW<[N2Write_10cyc_2V0], (instrs FDIVv2f32)>;
+def : InstRW<[N2Write_10c_2V0], (instrs FDIVv2f32)>;
// ASIMD FP divide, Q-form, F16
-def : InstRW<[N2Write_13cyc_2V0], (instrs FDIVv8f16)>;
+def : InstRW<[N2Write_13c_2V0], (instrs FDIVv8f16)>;
// ASIMD FP divide, Q-form, F32
-def : InstRW<[N2Write_10cyc_2V0], (instrs FDIVv4f32)>;
+def : InstRW<[N2Write_10c_2V0], (instrs FDIVv4f32)>;
// ASIMD FP divide, Q-form, F64
-def : InstRW<[N2Write_15cyc_2V0], (instrs FDIVv2f64)>;
+def : InstRW<[N2Write_15c_2V0], (instrs FDIVv2f64)>;
// ASIMD FP max/min, reduce, F32 and D-form F16
-def : InstRW<[N2Write_4cyc_1V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
// ASIMD FP max/min, reduce, Q-form F16
-def : InstRW<[N2Write_6cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
+def : InstRW<[N2Write_6c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
// ASIMD FP multiply
-def : InstRW<[N2Write_3cyc_1V], (instregex "^FMULv", "^FMULXv")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^FMULv", "^FMULXv")>;
// ASIMD FP multiply accumulate
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FMLAv", "^FMLSv")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FMLAv", "^FMLSv")>;
// ASIMD FP multiply accumulate long
-def : InstRW<[N2Write_5cyc_1V], (instregex "^FMLALv", "^FMLSLv")>;
+def : InstRW<[N2Write_5c_1V], (instregex "^FMLALv", "^FMLSLv")>;
// ASIMD FP round, D-form F32 and Q-form F64
-def : InstRW<[N2Write_3cyc_1V0],
+def : InstRW<[N2Write_3c_1V0],
(instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
"^FRINT[32|64)[XZ]v2f(32|64)$")>;
// ASIMD FP round, D-form F16 and Q-form F32
-def : InstRW<[N2Write_4cyc_2V0],
+def : InstRW<[N2Write_4c_2V0],
(instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
"^FRINT(32|64)[XZ]v4f32$")>;
// ASIMD FP round, Q-form F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
// ASIMD FP square root, D-form, F16
-def : InstRW<[N2Write_7cyc_1V0], (instrs FSQRTv4f16)>;
+def : InstRW<[N2Write_7c_1V0], (instrs FSQRTv4f16)>;
// ASIMD FP square root, D-form, F32
-def : InstRW<[N2Write_10cyc_2V0], (instrs FSQRTv2f32)>;
+def : InstRW<[N2Write_10c_2V0], (instrs FSQRTv2f32)>;
// ASIMD FP square root, Q-form, F16
-def : InstRW<[N2Write_13cyc_2V0], (instrs FSQRTv8f16)>;
+def : InstRW<[N2Write_13c_2V0], (instrs FSQRTv8f16)>;
// ASIMD FP square root, Q-form, F32
-def : InstRW<[N2Write_10cyc_2V0], (instrs FSQRTv4f32)>;
+def : InstRW<[N2Write_10c_2V0], (instrs FSQRTv4f32)>;
// ASIMD FP square root, Q-form, F64
-def : InstRW<[N2Write_16cyc_2V0], (instrs FSQRTv2f64)>;
+def : InstRW<[N2Write_16c_2V0], (instrs FSQRTv2f64)>;
// ASIMD BFloat16 (BF16) instructions
// -----------------------------------------------------------------------------
// ASIMD convert, F32 to BF16
-def : InstRW<[N2Write_4cyc_1V0], (instrs BFCVTN, BFCVTN2)>;
+def : InstRW<[N2Write_4c_1V0], (instrs BFCVTN, BFCVTN2)>;
// ASIMD dot product
-def : InstRW<[N2Write_4cyc_1V], (instrs BFDOTv4bf16, BFDOTv8bf16)>;
+def : InstRW<[N2Write_4c_1V], (instrs BFDOTv4bf16, BFDOTv8bf16)>;
// ASIMD matrix multiply accumulate
-def : InstRW<[N2Write_5cyc_1V], (instrs BFMMLA)>;
+def : InstRW<[N2Write_5c_1V], (instrs BFMMLA)>;
// ASIMD multiply accumulate long
-def : InstRW<[N2Write_4cyc_1V], (instrs BFMLALB, BFMLALBIdx, BFMLALT,
- BFMLALTIdx)>;
+def : InstRW<[N2Write_4c_1V], (instrs BFMLALB, BFMLALBIdx, BFMLALT,
+ BFMLALTIdx)>;
// Scalar convert, F32 to BF16
-def : InstRW<[N2Write_3cyc_1V0], (instrs BFCVT)>;
+def : InstRW<[N2Write_3c_1V0], (instrs BFCVT)>;
// ASIMD miscellaneous instructions
// -----------------------------------------------------------------------------
@@ -1185,412 +1185,412 @@ def : InstRW<[N2Write_3cyc_1V0], (instrs BFCVT)>;
// Handled by SchedAlias<WriteV[dq], ...>
// ASIMD duplicate, gen reg
-def : InstRW<[N2Write_3cyc_1M0], (instregex "^DUPv.+gpr")>;
+def : InstRW<[N2Write_3c_1M0], (instregex "^DUPv.+gpr")>;
// ASIMD extract narrow, saturating
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
// ASIMD reciprocal and square root estimate, D-form U32
-def : InstRW<[N2Write_3cyc_1V0], (instrs URECPEv2i32, URSQRTEv2i32)>;
+def : InstRW<[N2Write_3c_1V0], (instrs URECPEv2i32, URSQRTEv2i32)>;
// ASIMD reciprocal and square root estimate, Q-form U32
-def : InstRW<[N2Write_4cyc_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;
+def : InstRW<[N2Write_4c_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;
// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
-def : InstRW<[N2Write_3cyc_1V0], (instrs FRECPEv1f16, FRECPEv1i32,
- FRECPEv1i64, FRECPEv2f32,
- FRSQRTEv1f16, FRSQRTEv1i32,
- FRSQRTEv1i64, FRSQRTEv2f32)>;
+def : InstRW<[N2Write_3c_1V0], (instrs FRECPEv1f16, FRECPEv1i32,
+ FRECPEv1i64, FRECPEv2f32,
+ FRSQRTEv1f16, FRSQRTEv1i32,
+ FRSQRTEv1i64, FRSQRTEv2f32)>;
// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
-def : InstRW<[N2Write_4cyc_2V0], (instrs FRECPEv4f16, FRECPEv4f32,
+def : InstRW<[N2Write_4c_2V0], (instrs FRECPEv4f16, FRECPEv4f32,
FRSQRTEv4f16, FRSQRTEv4f32)>;
// ASIMD reciprocal and square root estimate, Q-form F16
-def : InstRW<[N2Write_6cyc_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
+def : InstRW<[N2Write_6c_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
// ASIMD reciprocal exponent
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRECPXv")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FRECPXv")>;
// ASIMD reciprocal step
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FRECPSv", "^FRSQRTSv")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FRECPSv", "^FRSQRTSv")>;
// ASIMD table lookup, 3 table regs
-def : InstRW<[N2Write_4cyc_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;
+def : InstRW<[N2Write_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;
// ASIMD table lookup, 4 table regs
-def : InstRW<[N2Write_4cyc_4V], (instrs TBLv8i8Four, TBLv16i8Four)>;
+def : InstRW<[N2Write_4c_4V], (instrs TBLv8i8Four, TBLv16i8Four)>;
// ASIMD table lookup extension, 2 table reg
-def : InstRW<[N2Write_4cyc_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;
+def : InstRW<[N2Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;
// ASIMD table lookup extension, 3 table reg
-def : InstRW<[N2Write_6cyc_4V], (instrs TBXv8i8Three, TBXv16i8Three)>;
+def : InstRW<[N2Write_6c_4V], (instrs TBXv8i8Three, TBXv16i8Three)>;
// ASIMD table lookup extension, 4 table reg
-def : InstRW<[N2Write_6cyc_8V], (instrs TBXv8i8Four, TBXv16i8Four)>;
+def : InstRW<[N2Write_6c_8V], (instrs TBXv8i8Four, TBXv16i8Four)>;
// ASIMD transfer, gen reg to element
-def : InstRW<[N2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
+def : InstRW<[N2Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
// ASIMD load instructions
// -----------------------------------------------------------------------------
// ASIMD load, 1 element, multiple, 1 reg, D-form
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_1L],
+def : InstRW<[N2Write_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_1L],
(instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 1 reg, Q-form
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_1L],
+def : InstRW<[N2Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_1L],
(instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 2 reg, D-form
-def : InstRW<[N2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_2L],
+def : InstRW<[N2Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_2L],
(instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 2 reg, Q-form
-def : InstRW<[N2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_2L],
+def : InstRW<[N2Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_2L],
(instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 3 reg, D-form
-def : InstRW<[N2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L],
+def : InstRW<[N2Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L],
(instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 3 reg, Q-form
-def : InstRW<[N2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L],
+def : InstRW<[N2Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L],
(instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 4 reg, D-form
-def : InstRW<[N2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_7cyc_4L],
+def : InstRW<[N2Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_7c_4L],
(instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 4 reg, Q-form
-def : InstRW<[N2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_7cyc_4L],
+def : InstRW<[N2Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_7c_4L],
(instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, one lane, B/H/S
// ASIMD load, 1 element, one lane, D
-def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
// ASIMD load, 1 element, all lanes, D-form, B/H/S
// ASIMD load, 1 element, all lanes, D-form, D
-def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, all lanes, Q-form
-def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 2 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
// ASIMD load, 2 element, multiple, Q-form, B/H/S
// ASIMD load, 2 element, multiple, Q-form, D
-def : InstRW<[N2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 2 element, one lane, B/H
// ASIMD load, 2 element, one lane, S
// ASIMD load, 2 element, one lane, D
-def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
// ASIMD load, 2 element, all lanes, D-form, B/H/S
// ASIMD load, 2 element, all lanes, D-form, D
-def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 2 element, all lanes, Q-form
-def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 3 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
// ASIMD load, 3 element, multiple, Q-form, B/H/S
-def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
+def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
// ASIMD load, 3 element, multiple, Q-form, D
-def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Threev(2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Threev(2d)_POST$")>;
+def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Threev(2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Threev(2d)_POST$")>;
// ASIMD load, 3 element, one lane, B/H
// ASIMD load, 3 element, one lane, S
// ASIMD load, 3 element, one lane, D
-def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
// ASIMD load, 3 element, all lanes, D-form, B/H/S
// ASIMD load, 3 element, all lanes, D-form, D
-def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 3 element, all lanes, Q-form, B/H/S
// ASIMD load, 3 element, all lanes, Q-form, D
-def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 4 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
// ASIMD load, 4 element, multiple, Q-form, B/H/S
// ASIMD load, 4 element, multiple, Q-form, D
-def : InstRW<[N2Write_9cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_9cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_9c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_9c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 4 element, one lane, B/H
// ASIMD load, 4 element, one lane, S
// ASIMD load, 4 element, one lane, D
-def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
// ASIMD load, 4 element, all lanes, D-form, B/H/S
// ASIMD load, 4 element, all lanes, D-form, D
-def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 4 element, all lanes, Q-form, B/H/S
// ASIMD load, 4 element, all lanes, Q-form, D
-def : InstRW<[N2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD store instructions
// -----------------------------------------------------------------------------
// ASIMD store, 1 element, multiple, 1 reg, D-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 1 reg, Q-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 2 reg, D-form
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 2 reg, Q-form
-def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 3 reg, D-form
-def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 3 reg, Q-form
-def : InstRW<[N2Write_2cyc_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_2c_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 4 reg, D-form
-def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 4 reg, Q-form
-def : InstRW<[N2Write_2cyc_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_2cyc_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_2c_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_2c_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, one lane, B/H/S
// ASIMD store, 1 element, one lane, D
-def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST1i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;
// ASIMD store, 2 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
// ASIMD store, 2 element, multiple, Q-form, B/H/S
// ASIMD store, 2 element, multiple, Q-form, D
-def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_4cyc_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_4c_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_4c_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 2 element, one lane, B/H/S
// ASIMD store, 2 element, one lane, D
-def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST2i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST2i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST2i(8|16|32|64)_POST$")>;
// ASIMD store, 3 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_5cyc_2L01_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_5cyc_2L01_2V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_5c_2L01_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_5c_2L01_2V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
// ASIMD store, 3 element, multiple, Q-form, B/H/S
// ASIMD store, 3 element, multiple, Q-form, D
-def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 3 element, one lane, B/H
// ASIMD store, 3 element, one lane, S
// ASIMD store, 3 element, one lane, D
-def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST3i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST3i(8|16|32|64)_POST$")>;
+def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST3i(8|16|32|64)_POST$")>;
// ASIMD store, 4 element, multiple, D-form, B/H/S
-def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
+def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
// ASIMD store, 4 element, multiple, Q-form, B/H/S
-def : InstRW<[N2Write_7cyc_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)$")>;
-def : InstRW<[WriteAdr, N2Write_7cyc_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
+def : InstRW<[N2Write_7c_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)$")>;
+def : InstRW<[WriteAdr, N2Write_7c_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
// ASIMD store, 4 element, multiple, Q-form, D
-def : InstRW<[N2Write_5cyc_4L01_4V], (instregex "ST4Fourv(2d)$")>;
-def : InstRW<[WriteAdr, N2Write_5cyc_4L01_4V], (instregex "ST4Fourv(2d)_POST$")>;
+def : InstRW<[N2Write_5c_4L01_4V], (instregex "ST4Fourv(2d)$")>;
+def : InstRW<[WriteAdr, N2Write_5c_4L01_4V], (instregex "ST4Fourv(2d)_POST$")>;
// ASIMD store, 4 element, one lane, B/H/S
-def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST4i(8|16|32)$")>;
-def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST4i(8|16|32)_POST$")>;
+def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST4i(8|16|32)$")>;
+def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST4i(8|16|32)_POST$")>;
// ASIMD store, 4 element, one lane, D
-def : InstRW<[N2Write_4cyc_3L01_3V], (instregex "ST4i(64)$")>;
-def : InstRW<[WriteAdr, N2Write_4cyc_3L01_3V], (instregex "ST4i(64)_POST$")>;
+def : InstRW<[N2Write_4c_3L01_3V], (instregex "ST4i(64)$")>;
+def : InstRW<[WriteAdr, N2Write_4c_3L01_3V], (instregex "ST4i(64)_POST$")>;
// Cryptography extensions
// -----------------------------------------------------------------------------
// Crypto AES ops
-def : InstRW<[N2Write_2cyc_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
// Crypto polynomial (64x64) multiply long
-def : InstRW<[N2Write_2cyc_1V0], (instrs PMULLv1i64, PMULLv2i64)>;
+def : InstRW<[N2Write_2c_1V0], (instrs PMULLv1i64, PMULLv2i64)>;
// Crypto SHA1 hash acceleration op
// Crypto SHA1 schedule acceleration ops
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^SHA1(H|SU0|SU1)")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;
// Crypto SHA1 hash acceleration ops
// Crypto SHA256 hash acceleration ops
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;
// Crypto SHA256 schedule acceleration ops
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^SHA256SU[01]")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^SHA256SU[01]")>;
// Crypto SHA512 hash acceleration ops
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;
// Crypto SHA3 ops
-def : InstRW<[N2Write_2cyc_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;
+def : InstRW<[N2Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;
// Crypto SM3 ops
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",
- "^SM3TT[12][AB]$")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",
+ "^SM3TT[12][AB]$")>;
// Crypto SM4 ops
-def : InstRW<[N2Write_4cyc_1V0], (instrs SM4E, SM4ENCKEY)>;
+def : InstRW<[N2Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;
// CRC
// -----------------------------------------------------------------------------
-def : InstRW<[N2Write_2cyc_1M0], (instregex "^CRC32")>;
+def : InstRW<[N2Write_2c_1M0], (instregex "^CRC32")>;
// SVE Predicate instructions
// -----------------------------------------------------------------------------
// Loop control, based on predicate
-def : InstRW<[N2Write_2cyc_1M], (instrs BRKA_PPmP, BRKA_PPzP,
- BRKB_PPmP, BRKB_PPzP)>;
+def : InstRW<[N2Write_2c_1M], (instrs BRKA_PPmP, BRKA_PPzP,
+ BRKB_PPmP, BRKB_PPzP)>;
// Loop control, based on predicate and flag setting
-def : InstRW<[N2Write_3cyc_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;
+def : InstRW<[N2Write_3c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;
// Loop control, propagating
-def : InstRW<[N2Write_2cyc_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;
+def : InstRW<[N2Write_2c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;
// Loop control, propagating and flag setting
-def : InstRW<[N2Write_3cyc_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,
- BRKPBS_PPzPP)>;
+def : InstRW<[N2Write_3c_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,
+ BRKPBS_PPzPP)>;
// Loop control, based on GPR
-def : InstRW<[N2Write_3cyc_1M],
+def : InstRW<[N2Write_3c_1M],
(instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>;
-def : InstRW<[N2Write_3cyc_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>;
// Loop terminate
-def : InstRW<[N2Write_1cyc_1M], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>;
+def : InstRW<[N2Write_1c_1M], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>;
// Predicate counting scalar
-def : InstRW<[N2Write_2cyc_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;
-def : InstRW<[N2Write_2cyc_1M],
+def : InstRW<[N2Write_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;
+def : InstRW<[N2Write_2c_1M],
(instregex "^(CNT|DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI$",
"^SQ(DEC|INC)[BHWD]_XPiWdI$",
"^(UQDEC|UQINC)[BHWD]_WPiI$")>;
// Predicate counting scalar, active predicate
-def : InstRW<[N2Write_2cyc_1M],
+def : InstRW<[N2Write_2c_1M],
(instregex "^CNTP_XPP_[BHSD]$",
"^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]$",
"^(UQDEC|UQINC)P_WP_[BHSD]$",
"^(SQDEC|SQINC|UQDEC|UQINC)P_XPWd_[BHSD]$")>;
// Predicate counting vector, active predicate
-def : InstRW<[N2Write_7cyc_1M_1M0_1V],
+def : InstRW<[N2Write_7c_1M_1M0_1V],
(instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]$")>;
// Predicate logical
-def : InstRW<[N2Write_1cyc_1M0],
+def : InstRW<[N2Write_1c_1M0],
(instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;
// Predicate logical, flag setting
-def : InstRW<[N2Write_2cyc_1M0_1M],
+def : InstRW<[N2Write_2c_1M0_1M],
(instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP$")>;
// Predicate reverse
-def : InstRW<[N2Write_2cyc_1M], (instregex "^REV_PP_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1M], (instregex "^REV_PP_[BHSD]$")>;
// Predicate select
-def : InstRW<[N2Write_1cyc_1M0], (instrs SEL_PPPP)>;
+def : InstRW<[N2Write_1c_1M0], (instrs SEL_PPPP)>;
// Predicate set
-def : InstRW<[N2Write_2cyc_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;
// Predicate set/initialize, set flags
-def : InstRW<[N2Write_3cyc_1M], (instregex "^PTRUES_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1M], (instregex "^PTRUES_[BHSD]$")>;
// Predicate find first/next
-def : InstRW<[N2Write_3cyc_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
// Predicate test
-def : InstRW<[N2Write_1cyc_1M], (instrs PTEST_PP)>;
+def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP)>;
// Predicate transpose
-def : InstRW<[N2Write_2cyc_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;
+def : InstRW<[N2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;
// Predicate unpack and widen
-def : InstRW<[N2Write_2cyc_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;
+def : InstRW<[N2Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;
// Predicate zip/unzip
-def : InstRW<[N2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;
+def : InstRW<[N2Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;
// SVE integer instructions
// -----------------------------------------------------------------------------
// Arithmetic, absolute
diff
-def : InstRW<[N2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
- "^[SU]ABD_ZPZZ_[BHSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
+ "^[SU]ABD_ZPZZ_[BHSD]")>;
// Arithmetic, absolute
diff accum
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
// Arithmetic, absolute
diff accum long
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;
// Arithmetic, absolute
diff long
-def : InstRW<[N2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;
// Arithmetic, basic
-def : InstRW<[N2Write_2cyc_1V],
+def : InstRW<[N2Write_2c_1V],
(instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
"^(ADD|SUB)_ZZZ_[BHSD]",
"^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",
@@ -1603,7 +1603,7 @@ def : InstRW<[N2Write_2cyc_1V],
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;
// Arithmetic, complex
-def : InstRW<[N2Write_2cyc_1V],
+def : InstRW<[N2Write_2c_1V],
(instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",
"^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",
@@ -1612,16 +1612,16 @@ def : InstRW<[N2Write_2cyc_1V],
"^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;
// Arithmetic, large integer
-def : InstRW<[N2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;
// Arithmetic, pairwise add
-def : InstRW<[N2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;
// Arithmetic, pairwise add and accum long
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;
// Arithmetic, shift
-def : InstRW<[N2Write_2cyc_1V1],
+def : InstRW<[N2Write_2c_1V1],
(instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
"^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
"^(ASR|LSL|LSR)_ZPmI_[BHSD]",
@@ -1631,16 +1631,16 @@ def : InstRW<[N2Write_2cyc_1V1],
"^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;
// Arithmetic, shift and accumulate
-def : InstRW<[N2Write_4cyc_1V1],
+def : InstRW<[N2Write_4c_1V1],
(instregex "^(SRSRA|SSRA|URSRA|USRA)_ZZI_[BHSD]$")>;
// Arithmetic, shift by immediate
// Arithmetic, shift by immediate and insert
-def : InstRW<[N2Write_2cyc_1V1],
+def : InstRW<[N2Write_2c_1V1],
(instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]$")>;
// Arithmetic, shift complex
-def : InstRW<[N2Write_4cyc_1V1],
+def : InstRW<[N2Write_4c_1V1],
(instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",
"^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",
"^[SU]QR?SHL_ZPZZ_[BHSD]",
@@ -1649,135 +1649,135 @@ def : InstRW<[N2Write_4cyc_1V1],
"^UQR?SHRN[BT]_ZZI_[BHS]")>;
// Arithmetic, shift right for divide
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;
// Arithmetic, shift rounding
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",
- "^[SU]RSHL_ZPZZ_[BHSD]",
- "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",
+ "^[SU]RSHL_ZPZZ_[BHSD]",
+ "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;
// Bit manipulation
-def : InstRW<[N2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;
+def : InstRW<[N2Write_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;
// Bitwise select
-def : InstRW<[N2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;
// Count/reverse bits
-def : InstRW<[N2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;
// Broadcast logical bitmask immediate to vector
-def : InstRW<[N2Write_2cyc_1V], (instrs DUPM_ZI)>;
+def : InstRW<[N2Write_2c_1V], (instrs DUPM_ZI)>;
// Compare and set flags
-def : InstRW<[N2Write_4cyc_1V0_1M],
+def : InstRW<[N2Write_4c_1V0_1M],
(instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$",
"^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>;
// Complex add
-def : InstRW<[N2Write_2cyc_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>;
// Complex dot product 8-bit element
-def : InstRW<[N2Write_3cyc_1V], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
+def : InstRW<[N2Write_3c_1V], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
// Complex dot product 16-bit element
-def : InstRW<[N2Write_4cyc_1V0], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
+def : InstRW<[N2Write_4c_1V0], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
// Complex multiply-add B, H, S element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^CMLA_ZZZ_[BHS]$",
- "^CMLA_ZZZI_[HS]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^CMLA_ZZZ_[BHS]$",
+ "^CMLA_ZZZI_[HS]$")>;
// Complex multiply-add D element size
-def : InstRW<[N2Write_5cyc_2V0], (instrs CMLA_ZZZ_D)>;
+def : InstRW<[N2Write_5c_2V0], (instrs CMLA_ZZZ_D)>;
// Conditional extract operations, scalar form
-def : InstRW<[N2Write_8cyc_1M0_1V1_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;
+def : InstRW<[N2Write_8c_1M0_1V1_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;
// Conditional extract operations, SIMD&FP scalar and vector forms
-def : InstRW<[N2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",
- "^COMPACT_ZPZ_[SD]$",
- "^SPLICE_ZPZZ?_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",
+ "^COMPACT_ZPZ_[SD]$",
+ "^SPLICE_ZPZZ?_[BHSD]$")>;
// Convert to floating point, 64b to float or convert to double
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",
- "^[SU]CVTF_ZPmZ_StoD")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",
+ "^[SU]CVTF_ZPmZ_StoD")>;
// Convert to floating point, 32b to single or half
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
// Convert to floating point, 16b to half
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;
// Copy, scalar
-def : InstRW<[N2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>;
+def : InstRW<[N2Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>;
// Copy, scalar SIMD&FP or imm
-def : InstRW<[N2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",
- "^CPY_ZPzI_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",
+ "^CPY_ZPzI_[BHSD]$")>;
// Divides, 32 bit
-def : InstRW<[N2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",
- "^[SU]DIV_ZPZZ_S")>;
+def : InstRW<[N2Write_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",
+ "^[SU]DIV_ZPZZ_S")>;
// Divides, 64 bit
-def : InstRW<[N2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",
- "^[SU]DIV_ZPZZ_D")>;
+def : InstRW<[N2Write_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",
+ "^[SU]DIV_ZPZZ_D")>;
// Dot product, 8 bit
-def : InstRW<[N2Write_3cyc_1V], (instregex "^[SU]DOT_ZZZI?_S$")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^[SU]DOT_ZZZI?_S$")>;
// Dot product, 8 bit, using signed and unsigned integers
-def : InstRW<[N2Write_3cyc_1V], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
+def : InstRW<[N2Write_3c_1V], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
// Dot product, 16 bit
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^[SU]DOT_ZZZI?_D$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]DOT_ZZZI?_D$")>;
// Duplicate, immediate and indexed form
-def : InstRW<[N2Write_2cyc_1V], (instregex "^DUP_ZI_[BHSD]$",
- "^DUP_ZZI_[BHSDQ]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^DUP_ZI_[BHSD]$",
+ "^DUP_ZZI_[BHSDQ]$")>;
// Duplicate, scalar form
-def : InstRW<[N2Write_3cyc_1M0], (instregex "^DUP_ZR_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>;
// Extend, sign or zero
-def : InstRW<[N2Write_2cyc_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",
- "^[SU]XTH_ZPmZ_[SD]",
- "^[SU]XTW_ZPmZ_[D]")>;
+def : InstRW<[N2Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",
+ "^[SU]XTH_ZPmZ_[SD]",
+ "^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[N2Write_2cyc_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[N2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
// Extract narrow saturating
-def : InstRW<[N2Write_4cyc_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",
- "^SQXTUN[BT]_ZZ_[BHS]$")>;
+def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",
+ "^SQXTUN[BT]_ZZ_[BHS]$")>;
// Extract/insert operation, SIMD and FP scalar form
-def : InstRW<[N2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",
- "^INSR_ZV_[BHSD]$")>;
+def : InstRW<[N2Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",
+ "^INSR_ZV_[BHSD]$")>;
// Extract/insert operation, scalar
-def : InstRW<[N2Write_5cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]$",
- "^INSR_ZR_[BHSD]$")>;
+def : InstRW<[N2Write_5c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]$",
+ "^INSR_ZR_[BHSD]$")>;
// Histogram operations
-def : InstRW<[N2Write_2cyc_1V], (instregex "^HISTCNT_ZPzZZ_[SD]$",
- "^HISTSEG_ZZZ$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]$",
+ "^HISTSEG_ZZZ$")>;
// Horizontal operations, B, H, S form, immediate operands only
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^INDEX_II_[BHS]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^INDEX_II_[BHS]$")>;
// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar
// operands only / immediate, scalar operands
-def : InstRW<[N2Write_7cyc_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>;
+def : InstRW<[N2Write_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>;
// Horizontal operations, D form, immediate operands only
-def : InstRW<[N2Write_5cyc_2V0], (instrs INDEX_II_D)>;
+def : InstRW<[N2Write_5c_2V0], (instrs INDEX_II_D)>;
// Horizontal operations, D form, scalar, immediate operands)/ scalar operands
// only / immediate, scalar operands
-def : InstRW<[N2Write_8cyc_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>;
+def : InstRW<[N2Write_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>;
// Logical
-def : InstRW<[N2Write_2cyc_1V],
+def : InstRW<[N2Write_2c_1V],
(instregex "^(AND|EOR|ORR)_ZI",
"^(AND|BIC|EOR|ORR)_ZZZ",
"^EOR(BT|TB)_ZZZ_[BHSD]",
@@ -1785,527 +1785,527 @@ def : InstRW<[N2Write_2cyc_1V],
"^NOT_ZPmZ_[BHSD]")>;
// Max/min, basic and pairwise
-def : InstRW<[N2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
- "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",
- "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
+ "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",
+ "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;
// Matching operations
-def : InstRW<[N2Write_2cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
+def : InstRW<[N2Write_2c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
// Matrix multiply-accumulate
-def : InstRW<[N2Write_3cyc_1V], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
+def : InstRW<[N2Write_3c_1V], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
// Move prefix
-def : InstRW<[N2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",
- "^MOVPRFX_ZZ$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",
+ "^MOVPRFX_ZZ$")>;
// Multiply, B, H, S element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",
- "^MUL_ZPZZ_[BHS]",
- "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",
- "^[SU]MULH_ZPZZ_[BHS]")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",
+ "^MUL_ZPZZ_[BHS]",
+ "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",
+ "^[SU]MULH_ZPZZ_[BHS]")>;
// Multiply, D element size
-def : InstRW<[N2Write_5cyc_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",
- "^MUL_ZPZZ_D",
- "^[SU]MULH_(ZPmZ|ZZZ)_D",
- "^[SU]MULH_ZPZZ_D")>;
+def : InstRW<[N2Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",
+ "^MUL_ZPZZ_D",
+ "^[SU]MULH_(ZPmZ|ZZZ)_D",
+ "^[SU]MULH_ZPZZ_D")>;
// Multiply long
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",
- "^[SU]MULL[BT]_ZZZ_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",
+ "^[SU]MULL[BT]_ZZZ_[HSD]$")>;
// Multiply accumulate, B, H, S element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^ML[AS]_ZZZI_[BHS]$",
- "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^ML[AS]_ZZZI_[BHS]$",
+ "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;
// Multiply accumulate, D element size
-def : InstRW<[N2Write_5cyc_2V0], (instregex "^ML[AS]_ZZZI_D$",
- "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
+def : InstRW<[N2Write_5c_2V0], (instregex "^ML[AS]_ZZZI_D$",
+ "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;
// Multiply accumulate long
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",
- "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",
+ "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;
// Multiply accumulate saturating doubling long regular
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",
- "^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",
+ "^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;
// Multiply saturating doubling high, B, H, S element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQDMULH_ZZZ_[BHS]$",
- "^SQDMULH_ZZZI_[HS]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMULH_ZZZ_[BHS]$",
+ "^SQDMULH_ZZZI_[HS]$")>;
// Multiply saturating doubling high, D element size
-def : InstRW<[N2Write_5cyc_2V0], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;
+def : InstRW<[N2Write_5c_2V0], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;
// Multiply saturating doubling long
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$",
- "^SQDMULL[BT]_ZZZI_[SD]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$",
+ "^SQDMULL[BT]_ZZZI_[SD]$")>;
// Multiply saturating rounding doubling regular/complex accumulate, B, H, S
// element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",
- "^SQRDCMLAH_ZZZ_[BHS]$",
- "^SQRDML[AS]H_ZZZI_[HS]$",
- "^SQRDCMLAH_ZZZI_[HS]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",
+ "^SQRDCMLAH_ZZZ_[BHS]$",
+ "^SQRDML[AS]H_ZZZI_[HS]$",
+ "^SQRDCMLAH_ZZZI_[HS]$")>;
// Multiply saturating rounding doubling regular/complex accumulate, D element
// size
-def : InstRW<[N2Write_5cyc_2V0], (instregex "^SQRDML[AS]H_ZZZI?_D$",
- "^SQRDCMLAH_ZZZ_D$")>;
+def : InstRW<[N2Write_5c_2V0], (instregex "^SQRDML[AS]H_ZZZI?_D$",
+ "^SQRDCMLAH_ZZZ_D$")>;
// Multiply saturating rounding doubling regular/complex, B, H, S element size
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SQRDMULH_ZZZ_[BHS]$",
- "^SQRDMULH_ZZZI_[HS]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDMULH_ZZZ_[BHS]$",
+ "^SQRDMULH_ZZZI_[HS]$")>;
// Multiply saturating rounding doubling regular/complex, D element size
-def : InstRW<[N2Write_5cyc_2V0], (instregex "^SQRDMULH_ZZZI?_D$")>;
+def : InstRW<[N2Write_5c_2V0], (instregex "^SQRDMULH_ZZZI?_D$")>;
// Multiply/multiply long, (8x8) polynomial
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^PMUL_ZZZ_B$",
- "^PMULL[BT]_ZZZ_[HDQ]$")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^PMUL_ZZZ_B$",
+ "^PMULL[BT]_ZZZ_[HDQ]$")>;
// Predicate counting vector
-def : InstRW<[N2Write_2cyc_1V0],
+def : InstRW<[N2Write_2c_1V0],
(instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[HWD]_ZPiI$")>;
// Reciprocal estimate
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
// Reduction, arithmetic, B form
-def : InstRW<[N2Write_11cyc_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
+def : InstRW<[N2Write_11c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
// Reduction, arithmetic, H form
-def : InstRW<[N2Write_9cyc_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;
+def : InstRW<[N2Write_9c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;
// Reduction, arithmetic, S form
-def : InstRW<[N2Write_8cyc_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;
+def : InstRW<[N2Write_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;
// Reduction, arithmetic, D form
-def : InstRW<[N2Write_8cyc_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
+def : InstRW<[N2Write_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
// Reduction, logical
-def : InstRW<[N2Write_6cyc_1V_1V1], (instregex "^(ANDV|EORV|ORV)_VPZ_[BHSD]$")>;
+def : InstRW<[N2Write_6c_1V_1V1], (instregex "^(ANDV|EORV|ORV)_VPZ_[BHSD]$")>;
// Reverse, vector
-def : InstRW<[N2Write_2cyc_1V], (instregex "^REV_ZZ_[BHSD]$",
- "^REVB_ZPmZ_[HSD]$",
- "^REVH_ZPmZ_[SD]$",
- "^REVW_ZPmZ_D$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^REV_ZZ_[BHSD]$",
+ "^REVB_ZPmZ_[HSD]$",
+ "^REVH_ZPmZ_[SD]$",
+ "^REVW_ZPmZ_D$")>;
// Select, vector form
-def : InstRW<[N2Write_2cyc_1V], (instregex "^SEL_ZPZZ_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]$")>;
// Table lookup
-def : InstRW<[N2Write_2cyc_1V], (instregex "^TBL_ZZZZ?_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]$")>;
// Table lookup extension
-def : InstRW<[N2Write_2cyc_1V], (instregex "^TBX_ZZZ_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^TBX_ZZZ_[BHSD]$")>;
// Transpose, vector form
-def : InstRW<[N2Write_2cyc_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]$")>;
// Unpack and extend
-def : InstRW<[N2Write_2cyc_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]$")>;
// Zip/unzip
-def : InstRW<[N2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;
// SVE floating-point instructions
// -----------------------------------------------------------------------------
// Floating point absolute value/
diff erence
-def : InstRW<[N2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",
- "^FABD_ZPZZ_[HSD]",
- "^FABS_ZPmZ_[HSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",
+ "^FABD_ZPZZ_[HSD]",
+ "^FABS_ZPmZ_[HSD]")>;
// Floating point arithmetic
-def : InstRW<[N2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",
- "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",
- "^FADDP_ZPmZZ_[HSD]",
- "^FNEG_ZPmZ_[HSD]",
- "^FSUBR_ZPm[IZ]_[HSD]",
- "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",
+ "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",
+ "^FADDP_ZPmZZ_[HSD]",
+ "^FNEG_ZPmZ_[HSD]",
+ "^FSUBR_ZPm[IZ]_[HSD]",
+ "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;
// Floating point associative add, F16
-def : InstRW<[N2Write_10cyc_1V1], (instrs FADDA_VPZ_H)>;
+def : InstRW<[N2Write_10c_1V1], (instrs FADDA_VPZ_H)>;
// Floating point associative add, F32
-def : InstRW<[N2Write_6cyc_1V1], (instrs FADDA_VPZ_S)>;
+def : InstRW<[N2Write_6c_1V1], (instrs FADDA_VPZ_S)>;
// Floating point associative add, F64
-def : InstRW<[N2Write_4cyc_1V], (instrs FADDA_VPZ_D)>;
+def : InstRW<[N2Write_4c_1V], (instrs FADDA_VPZ_D)>;
// Floating point compare
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]$",
- "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]$",
- "^FCM(LE|LT)_PPzZ0_[HSD]$",
- "^FCMUO_PPzZZ_[HSD]$")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]$",
+ "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]$",
+ "^FCM(LE|LT)_PPzZ0_[HSD]$",
+ "^FCMUO_PPzZZ_[HSD]$")>;
// Floating point complex add
-def : InstRW<[N2Write_3cyc_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>;
// Floating point complex multiply add
-def : InstRW<[N2Write_5cyc_1V], (instregex "^FCMLA_ZPmZZ_[HSD]$",
- "^FCMLA_ZZZI_[HS]$")>;
+def : InstRW<[N2Write_5c_1V], (instregex "^FCMLA_ZPmZZ_[HSD]$",
+ "^FCMLA_ZZZI_[HS]$")>;
// Floating point convert, long or narrow (F16 to F32 or F32 to F16)
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
- "^FCVTLT_ZPmZ_HtoS",
- "^FCVTNT_ZPmZ_StoH")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
+ "^FCVTLT_ZPmZ_HtoS",
+ "^FCVTNT_ZPmZ_StoH")>;
// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32
// or F64 to F16)
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",
- "^FCVTLT_ZPmZ_StoD",
- "^FCVTNT_ZPmZ_DtoS")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",
+ "^FCVTLT_ZPmZ_StoD",
+ "^FCVTNT_ZPmZ_DtoS")>;
// Floating point convert, round to odd
-def : InstRW<[N2Write_3cyc_1V0], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;
+def : InstRW<[N2Write_3c_1V0], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;
// Floating point base2 log, F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;
// Floating point base2 log, F32
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;
// Floating point base2 log, F64
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;
// Floating point convert to integer, F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;
// Floating point convert to integer, F32
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;
// Floating point convert to integer, F64
-def : InstRW<[N2Write_3cyc_1V0],
+def : InstRW<[N2Write_3c_1V0],
(instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;
// Floating point copy
-def : InstRW<[N2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]$",
- "^FDUP_ZI_[HSD]$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]$",
+ "^FDUP_ZI_[HSD]$")>;
// Floating point divide, F16
-def : InstRW<[N2Write_13cyc_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;
+def : InstRW<[N2Write_13c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;
// Floating point divide, F32
-def : InstRW<[N2Write_10cyc_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;
+def : InstRW<[N2Write_10c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;
// Floating point divide, F64
-def : InstRW<[N2Write_15cyc_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;
+def : InstRW<[N2Write_15c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;
// Floating point min/max pairwise
-def : InstRW<[N2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;
// Floating point min/max
-def : InstRW<[N2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",
- "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",
+ "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;
// Floating point multiply
-def : InstRW<[N2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
- "^FMULX_ZPZZ_[HSD]",
- "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",
- "^FMUL_ZPZ[IZ]_[HSD]")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
+ "^FMULX_ZPZZ_[HSD]",
+ "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",
+ "^FMUL_ZPZ[IZ]_[HSD]")>;
// Floating point multiply accumulate
-def : InstRW<[N2Write_4cyc_1V], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$",
- "^FN?ML[AS]_ZPZZZ_[HSD]",
- "^FML[AS]_ZZZI_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$",
+ "^FN?ML[AS]_ZPZZZ_[HSD]",
+ "^FML[AS]_ZZZI_[HSD]$")>;
// Floating point multiply add/sub accumulate long
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
// Floating point reciprocal estimate, F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
// Floating point reciprocal estimate, F32
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;
// Floating point reciprocal estimate, F64
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;
// Floating point reciprocal step
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;
// Floating point reduction, F16
-def : InstRW<[N2Write_6cyc_2V],
+def : InstRW<[N2Write_6c_2V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>;
// Floating point reduction, F32
-def : InstRW<[N2Write_4cyc_1V],
+def : InstRW<[N2Write_4c_1V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>;
// Floating point reduction, F64
-def : InstRW<[N2Write_2cyc_1V],
+def : InstRW<[N2Write_2c_1V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>;
// Floating point round to integral, F16
-def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
+def : InstRW<[N2Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
// Floating point round to integral, F32
-def : InstRW<[N2Write_4cyc_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
+def : InstRW<[N2Write_4c_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
// Floating point round to integral, F64
-def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
+def : InstRW<[N2Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
// Floating point square root, F16
-def : InstRW<[N2Write_13cyc_1V0], (instregex "^FSQRT_ZPmZ_H")>;
+def : InstRW<[N2Write_13c_1V0], (instregex "^FSQRT_ZPmZ_H")>;
// Floating point square root, F32
-def : InstRW<[N2Write_10cyc_1V0], (instregex "^FSQRT_ZPmZ_S")>;
+def : InstRW<[N2Write_10c_1V0], (instregex "^FSQRT_ZPmZ_S")>;
// Floating point square root, F64
-def : InstRW<[N2Write_16cyc_1V0], (instregex "^FSQRT_ZPmZ_D")>;
+def : InstRW<[N2Write_16c_1V0], (instregex "^FSQRT_ZPmZ_D")>;
// Floating point trigonometric exponentiation
-def : InstRW<[N2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>;
+def : InstRW<[N2Write_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>;
// Floating point trigonometric multiply add
-def : InstRW<[N2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]$")>;
// Floating point trigonometric, miscellaneous
-def : InstRW<[N2Write_3cyc_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;
+def : InstRW<[N2Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;
// SVE BFloat16 (BF16) instructions
// -----------------------------------------------------------------------------
// Convert, F32 to BF16
-def : InstRW<[N2Write_3cyc_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
+def : InstRW<[N2Write_3c_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
// Dot product
-def : InstRW<[N2Write_4cyc_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
+def : InstRW<[N2Write_4c_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
// Matrix multiply accumulate
-def : InstRW<[N2Write_5cyc_1V], (instrs BFMMLA_ZZZ)>;
+def : InstRW<[N2Write_5c_1V], (instrs BFMMLA_ZZZ)>;
// Multiply accumulate long
-def : InstRW<[N2Write_4cyc_1V], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;
+def : InstRW<[N2Write_4c_1V], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;
// SVE Load instructions
// -----------------------------------------------------------------------------
// Load vector
-def : InstRW<[N2Write_6cyc_1L], (instrs LDR_ZXI)>;
+def : InstRW<[N2Write_6c_1L], (instrs LDR_ZXI)>;
// Load predicate
-def : InstRW<[N2Write_6cyc_1L_1M], (instrs LDR_PXI)>;
+def : InstRW<[N2Write_6c_1L_1M], (instrs LDR_PXI)>;
// Contiguous load, scalar + imm
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
- "^LD1S?B_[HSD]_IMM$",
- "^LD1S?H_[SD]_IMM$",
- "^LD1S?W_D_IMM$" )>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",
+ "^LD1S?B_[HSD]_IMM$",
+ "^LD1S?H_[SD]_IMM$",
+ "^LD1S?W_D_IMM$" )>;
// Contiguous load, scalar + scalar
-def : InstRW<[N2Write_6cyc_1L01], (instregex "^LD1[BHWD]$",
- "^LD1S?B_[HSD]$",
- "^LD1S?H_[SD]$",
- "^LD1S?W_D$" )>;
+def : InstRW<[N2Write_6c_1L01], (instregex "^LD1[BHWD]$",
+ "^LD1S?B_[HSD]$",
+ "^LD1S?H_[SD]$",
+ "^LD1S?W_D$" )>;
// Contiguous load broadcast, scalar + imm
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1R[BHWD]_IMM$",
- "^LD1RSW_IMM$",
- "^LD1RS?B_[HSD]_IMM$",
- "^LD1RS?H_[SD]_IMM$",
- "^LD1RS?W_D_IMM$",
- "^LD1RQ_[BHWD]_IMM$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",
+ "^LD1RSW_IMM$",
+ "^LD1RS?B_[HSD]_IMM$",
+ "^LD1RS?H_[SD]_IMM$",
+ "^LD1RS?W_D_IMM$",
+ "^LD1RQ_[BHWD]_IMM$")>;
// Contiguous load broadcast, scalar + scalar
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1RQ_[BHWD]$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;
// Non temporal load, scalar + imm
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LDNT1[BHWD]_ZRI$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LDNT1[BHWD]_ZRI$")>;
// Non temporal load, scalar + scalar
-def : InstRW<[N2Write_6cyc_1L_1S], (instregex "^LDNT1[BHWD]_ZRR$")>;
+def : InstRW<[N2Write_6c_1L_1S], (instregex "^LDNT1[BHWD]_ZRR$")>;
// Non temporal gather load, vector + scalar 32-bit element size
-def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^LDNT1[BHW]_ZZR_S$",
- "^LDNT1S[BH]_ZZR_S$")>;
+def : InstRW<[N2Write_9c_1L_1V], (instregex "^LDNT1[BHW]_ZZR_S$",
+ "^LDNT1S[BH]_ZZR_S$")>;
// Non temporal gather load, vector + scalar 64-bit element size
-def : InstRW<[N2Write_10cyc_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;
-def : InstRW<[N2Write_10cyc_2L_2V1], (instrs LDNT1D_ZZR_D)>;
+def : InstRW<[N2Write_10c_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;
+def : InstRW<[N2Write_10c_2L_2V1], (instrs LDNT1D_ZZR_D)>;
// Contiguous first faulting load, scalar + scalar
-def : InstRW<[N2Write_6cyc_1L_1S], (instregex "^LDFF1[BHWD]$",
- "^LDFF1S?B_[HSD]$",
- "^LDFF1S?H_[SD]$",
- "^LDFF1S?W_D$")>;
+def : InstRW<[N2Write_6c_1L_1S], (instregex "^LDFF1[BHWD]$",
+ "^LDFF1S?B_[HSD]$",
+ "^LDFF1S?H_[SD]$",
+ "^LDFF1S?W_D$")>;
// Contiguous non faulting load, scalar + imm
-def : InstRW<[N2Write_6cyc_1L], (instregex "^LDNF1[BHWD]_IMM$",
- "^LDNF1S?B_[HSD]_IMM$",
- "^LDNF1S?H_[SD]_IMM$",
- "^LDNF1S?W_D_IMM$")>;
+def : InstRW<[N2Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",
+ "^LDNF1S?B_[HSD]_IMM$",
+ "^LDNF1S?H_[SD]_IMM$",
+ "^LDNF1S?W_D_IMM$")>;
// Contiguous Load two structures to two vectors, scalar + imm
-def : InstRW<[N2Write_8cyc_1L_1V], (instregex "^LD2[BHWD]_IMM$")>;
+def : InstRW<[N2Write_8c_1L_1V], (instregex "^LD2[BHWD]_IMM$")>;
// Contiguous Load two structures to two vectors, scalar + scalar
-def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^LD2[BHWD]$")>;
+def : InstRW<[N2Write_9c_1L_1V], (instregex "^LD2[BHWD]$")>;
// Contiguous Load three structures to three vectors, scalar + imm
-def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^LD3[BHWD]_IMM$")>;
+def : InstRW<[N2Write_9c_1L_1V], (instregex "^LD3[BHWD]_IMM$")>;
// Contiguous Load three structures to three vectors, scalar + scalar
-def : InstRW<[N2Write_10cyc_1V_1L_1S], (instregex "^LD3[BHWD]$")>;
+def : InstRW<[N2Write_10c_1V_1L_1S], (instregex "^LD3[BHWD]$")>;
// Contiguous Load four structures to four vectors, scalar + imm
-def : InstRW<[N2Write_9cyc_2L_2V], (instregex "^LD4[BHWD]_IMM$")>;
+def : InstRW<[N2Write_9c_2L_2V], (instregex "^LD4[BHWD]_IMM$")>;
// Contiguous Load four structures to four vectors, scalar + scalar
-def : InstRW<[N2Write_10cyc_2L_2V_2S], (instregex "^LD4[BHWD]$")>;
+def : InstRW<[N2Write_10c_2L_2V_2S], (instregex "^LD4[BHWD]$")>;
// Gather load, vector + imm, 32-bit element size
-def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
- "^GLD(FF)?1W_IMM$")>;
+def : InstRW<[N2Write_9c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
+ "^GLD(FF)?1W_IMM$")>;
// Gather load, vector + imm, 64-bit element size
-def : InstRW<[N2Write_9cyc_2L_2V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",
- "^GLD(FF)?1D_IMM$")>;
+def : InstRW<[N2Write_9c_2L_2V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",
+ "^GLD(FF)?1D_IMM$")>;
// Gather load, 64-bit element size
-def : InstRW<[N2Write_9cyc_2L_2V],
+def : InstRW<[N2Write_9c_2L_2V],
(instregex "^GLD(FF)?1S?[BHW]_D_[SU]XTW(_SCALED)?$",
"^GLD(FF)?1S?[BHW]_D(_SCALED)?$",
"^GLD(FF)?1D_[SU]XTW(_SCALED)?$",
"^GLD(FF)?1D(_SCALED)?$")>;
// Gather load, 32-bit scaled offset
-def : InstRW<[N2Write_10cyc_2L_2V],
+def : InstRW<[N2Write_10c_2L_2V],
(instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED$",
"^GLD(FF)?1W_[SU]XTW_SCALED")>;
// Gather load, 32-bit unpacked unscaled offset
-def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
- "^GLD(FF)?1W_[SU]XTW$")>;
+def : InstRW<[N2Write_9c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
+ "^GLD(FF)?1W_[SU]XTW$")>;
// SVE Store instructions
// -----------------------------------------------------------------------------
// Store from predicate reg
-def : InstRW<[N2Write_1cyc_1L01], (instrs STR_PXI)>;
+def : InstRW<[N2Write_1c_1L01], (instrs STR_PXI)>;
// Store from vector reg
-def : InstRW<[N2Write_2cyc_1L01_1V], (instrs STR_ZXI)>;
+def : InstRW<[N2Write_2c_1L01_1V], (instrs STR_ZXI)>;
// Contiguous store, scalar + imm
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
- "^ST1B_[HSD]_IMM$",
- "^ST1H_[SD]_IMM$",
- "^ST1W_D_IMM$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
+ "^ST1B_[HSD]_IMM$",
+ "^ST1H_[SD]_IMM$",
+ "^ST1W_D_IMM$")>;
// Contiguous store, scalar + scalar
-def : InstRW<[N2Write_2cyc_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>;
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BWD]$",
- "^ST1B_[HSD]$",
- "^ST1W_D$")>;
+def : InstRW<[N2Write_2c_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BWD]$",
+ "^ST1B_[HSD]$",
+ "^ST1W_D$")>;
// Contiguous store two structures from two vectors, scalar + imm
-def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "^ST2[BHWD]_IMM$")>;
+def : InstRW<[N2Write_4c_1L01_1V], (instregex "^ST2[BHWD]_IMM$")>;
// Contiguous store two structures from two vectors, scalar + scalar
-def : InstRW<[N2Write_4cyc_1L01_1S_1V], (instrs ST2H)>;
+def : InstRW<[N2Write_4c_1L01_1S_1V], (instrs ST2H)>;
// Contiguous store two structures from two vectors, scalar + scalar
-def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "^ST2[BWD]$")>;
+def : InstRW<[N2Write_4c_1L01_1V], (instregex "^ST2[BWD]$")>;
// Contiguous store three structures from three vectors, scalar + imm
-def : InstRW<[N2Write_7cyc_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>;
+def : InstRW<[N2Write_7c_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>;
// Contiguous store three structures from three vectors, scalar + scalar
-def : InstRW<[N2Write_7cyc_5L01_5S_5V], (instrs ST3H)>;
+def : InstRW<[N2Write_7c_5L01_5S_5V], (instrs ST3H)>;
// Contiguous store three structures from three vectors, scalar + scalar
-def : InstRW<[N2Write_7cyc_5L01_5S_5V], (instregex "^ST3[BWD]$")>;
+def : InstRW<[N2Write_7c_5L01_5S_5V], (instregex "^ST3[BWD]$")>;
// Contiguous store four structures from four vectors, scalar + imm
-def : InstRW<[N2Write_11cyc_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>;
+def : InstRW<[N2Write_11c_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>;
// Contiguous store four structures from four vectors, scalar + scalar
-def : InstRW<[N2Write_11cyc_9L01_9S_9V], (instrs ST4H)>;
+def : InstRW<[N2Write_11c_9L01_9S_9V], (instrs ST4H)>;
// Contiguous store four structures from four vectors, scalar + scalar
-def : InstRW<[N2Write_11cyc_9L01_9S_9V], (instregex "^ST4[BWD]$")>;
+def : InstRW<[N2Write_11c_9L01_9S_9V], (instregex "^ST4[BWD]$")>;
// Non temporal store, scalar + imm
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;
// Non temporal store, scalar + scalar
-def : InstRW<[N2Write_2cyc_1L01_1S_1V], (instrs STNT1H_ZRR)>;
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>;
+def : InstRW<[N2Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>;
// Scatter non temporal store, vector + scalar 32-bit element size
-def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^STNT1[BHW]_ZZR_S")>;
+def : InstRW<[N2Write_4c_2L01_2V], (instregex "^STNT1[BHW]_ZZR_S")>;
// Scatter non temporal store, vector + scalar 64-bit element size
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^STNT1[BHWD]_ZZR_D")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZZR_D")>;
// Scatter store vector + imm 32-bit element size
-def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_IMM$",
- "^SST1W_IMM$")>;
+def : InstRW<[N2Write_4c_2L01_2V], (instregex "^SST1[BH]_S_IMM$",
+ "^SST1W_IMM$")>;
// Scatter store vector + imm 64-bit element size
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[BHW]_D_IMM$",
- "^SST1D_IMM$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$",
+ "^SST1D_IMM$")>;
// Scatter store, 32-bit scaled offset
-def : InstRW<[N2Write_4cyc_2L01_2V],
+def : InstRW<[N2Write_4c_2L01_2V],
(instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;
// Scatter store, 32-bit unpacked unscaled offset
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$",
- "^SST1D_[SU]XTW$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$",
+ "^SST1D_[SU]XTW$")>;
// Scatter store, 32-bit unpacked scaled offset
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
- "^SST1D_[SU]XTW_SCALED$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
+ "^SST1D_[SU]XTW_SCALED$")>;
// Scatter store, 32-bit unscaled offset
-def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",
- "^SST1W_[SU]XTW$")>;
+def : InstRW<[N2Write_4c_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",
+ "^SST1W_[SU]XTW$")>;
// Scatter store, 64-bit scaled offset
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[HW]_D_SCALED$",
- "^SST1D_SCALED$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[HW]_D_SCALED$",
+ "^SST1D_SCALED$")>;
// Scatter store, 64-bit unscaled offset
-def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^SST1[BHW]_D$",
- "^SST1D$")>;
+def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D$",
+ "^SST1D$")>;
// SVE Miscellaneous instructions
// -----------------------------------------------------------------------------
// Read first fault register, unpredicated
-def : InstRW<[N2Write_2cyc_1M0], (instrs RDFFR_P)>;
+def : InstRW<[N2Write_2c_1M0], (instrs RDFFR_P)>;
// Read first fault register, predicated
-def : InstRW<[N2Write_3cyc_1M0_1M], (instrs RDFFR_PPz)>;
+def : InstRW<[N2Write_3c_1M0_1M], (instrs RDFFR_PPz)>;
// Read first fault register and set flags
-def : InstRW<[N2Write_4cyc_2M0_2M], (instrs RDFFRS_PPz)>;
+def : InstRW<[N2Write_4c_2M0_2M], (instrs RDFFRS_PPz)>;
// Set first fault register
// Write to first fault register
-def : InstRW<[N2Write_2cyc_1M0], (instrs SETFFR, WRFFR)>;
+def : InstRW<[N2Write_2c_1M0], (instrs SETFFR, WRFFR)>;
// Prefetch
-def : InstRW<[N2Write_4cyc_1L], (instregex "^PRF[BHWD]")>;
+def : InstRW<[N2Write_4c_1L], (instregex "^PRF[BHWD]")>;
// SVE Cryptographic instructions
// -----------------------------------------------------------------------------
// Crypto AES ops
-def : InstRW<[N2Write_2cyc_1V], (instregex "^AES[DE]_ZZZ_B$",
- "^AESI?MC_ZZ_B$")>;
+def : InstRW<[N2Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",
+ "^AESI?MC_ZZ_B$")>;
// Crypto SHA3 ops
-def : InstRW<[N2Write_2cyc_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",
- "^RAX1_ZZZ_D$",
- "^XAR_ZZZI_[BHSD]$")>;
+def : InstRW<[N2Write_2c_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",
+ "^RAX1_ZZZ_D$",
+ "^XAR_ZZZI_[BHSD]$")>;
// Crypto SM4 ops
-def : InstRW<[N2Write_4cyc_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
+def : InstRW<[N2Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 66f3914809490e..f884d20ab7eda9 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -91,292 +91,292 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
//===----------------------------------------------------------------------===//
// Define generic 0 micro-op types
-def V2Write_0cyc : SchedWriteRes<[]> { let Latency = 0; }
+def V2Write_0c : SchedWriteRes<[]> { let Latency = 0; }
// Define generic 1 micro-op types
-def V2Write_1cyc_1B : SchedWriteRes<[V2UnitB]> { let Latency = 1; }
-def V2Write_1cyc_1F : SchedWriteRes<[V2UnitF]> { let Latency = 1; }
-def V2Write_1cyc_1I : SchedWriteRes<[V2UnitI]> { let Latency = 1; }
-def V2Write_1cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 1; }
-def V2Write_1cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 1; }
-def V2Write_1cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 1; }
-def V2Write_2cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 2; }
-def V2Write_3cyc_1M : SchedWriteRes<[V2UnitM]> { let Latency = 3; }
-def V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
-def V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }
-def V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }
-def V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;
- let ReleaseAtCycles = [12]; }
-def V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
-def V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }
-def V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }
-def V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }
-def V2Write_2cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 2; }
-def V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
-def V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
-def V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }
-def V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
- let ReleaseAtCycles = [2]; }
-def V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
-def V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }
-def V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
-def V2Write_6cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 6; }
-def V2Write_12cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 12; }
-def V2Write_3cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 3; }
-def V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
-def V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }
-def V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
-def V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;
- let ReleaseAtCycles = [7]; }
-def V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
- let ReleaseAtCycles = [2]; }
-def V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }
-def V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
- let ReleaseAtCycles = [2]; }
-def V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }
-def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
- let ReleaseAtCycles = [2]; }
-def V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;
- let ReleaseAtCycles = [11]; }
-def V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }
-def V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }
-def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
- let ReleaseAtCycles = [8]; }
-def V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }
-def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
- let ReleaseAtCycles = [8]; }
-def V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;
- let ReleaseAtCycles = [20]; }
-def V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }
-def V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
-def V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }
-def V2Write_4cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 4; }
-def V2Write_4cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }
-def V2Write_6cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 6; }
-def V2Write_10cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 10; }
-def V2Write_6cyc_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 6; }
+def V2Write_1c_1B : SchedWriteRes<[V2UnitB]> { let Latency = 1; }
+def V2Write_1c_1F : SchedWriteRes<[V2UnitF]> { let Latency = 1; }
+def V2Write_1c_1I : SchedWriteRes<[V2UnitI]> { let Latency = 1; }
+def V2Write_1c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 1; }
+def V2Write_1c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 1; }
+def V2Write_1c_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 1; }
+def V2Write_2c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 2; }
+def V2Write_3c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 3; }
+def V2Write_2c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
+def V2Write_3c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }
+def V2Write_5c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }
+def V2Write_12c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;
+ let ReleaseAtCycles = [12]; }
+def V2Write_20c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;
+ let ReleaseAtCycles = [20]; }
+def V2Write_4c_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }
+def V2Write_6c_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }
+def V2Write_2c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }
+def V2Write_2c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 2; }
+def V2Write_2c_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
+def V2Write_2c_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
+def V2Write_3c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }
+def V2Write_3c_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
+ let ReleaseAtCycles = [2]; }
+def V2Write_3c_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
+def V2Write_4c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }
+def V2Write_5c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
+def V2Write_6c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 6; }
+def V2Write_12c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 12; }
+def V2Write_3c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 3; }
+def V2Write_3c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
+def V2Write_4c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }
+def V2Write_4c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
+def V2Write_7c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;
+ let ReleaseAtCycles = [7]; }
+def V2Write_7c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
+ let ReleaseAtCycles = [2]; }
+def V2Write_9c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }
+def V2Write_9c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
+ let ReleaseAtCycles = [2]; }
+def V2Write_10c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }
+def V2Write_10c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
+ let ReleaseAtCycles = [2]; }
+def V2Write_12c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;
+ let ReleaseAtCycles = [11]; }
+def V2Write_13c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }
+def V2Write_15c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }
+def V2Write_15c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
+ let ReleaseAtCycles = [8]; }
+def V2Write_16c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }
+def V2Write_16c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
+ let ReleaseAtCycles = [8]; }
+def V2Write_20c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;
+ let ReleaseAtCycles = [20]; }
+def V2Write_2c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }
+def V2Write_2c_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
+def V2Write_3c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }
+def V2Write_4c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 4; }
+def V2Write_4c_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }
+def V2Write_6c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 6; }
+def V2Write_10c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 10; }
+def V2Write_6c_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 6; }
//===----------------------------------------------------------------------===//
// Define generic 2 micro-op types
-def V2Write_1cyc_1B_1R : SchedWriteRes<[V2UnitB, V2UnitR]> {
+def V2Write_1c_1B_1R : SchedWriteRes<[V2UnitB, V2UnitR]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1M0_1B : SchedWriteRes<[V2UnitM0, V2UnitB]> {
+def V2Write_6c_1M0_1B : SchedWriteRes<[V2UnitM0, V2UnitB]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_9cyc_1M0_1L : SchedWriteRes<[V2UnitM0, V2UnitL]> {
+def V2Write_9c_1M0_1L : SchedWriteRes<[V2UnitM0, V2UnitL]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def V2Write_3cyc_1I_1M : SchedWriteRes<[V2UnitI, V2UnitM]> {
+def V2Write_3c_1I_1M : SchedWriteRes<[V2UnitI, V2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def V2Write_1cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
+def V2Write_1c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def V2Write_3cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
+def V2Write_3c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
+def V2Write_4c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_5cyc_1L_1F : SchedWriteRes<[V2UnitL, V2UnitF]> {
+def V2Write_5c_1L_1F : SchedWriteRes<[V2UnitL, V2UnitF]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {
+def V2Write_6c_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_7cyc_1F_1L : SchedWriteRes<[V2UnitF, V2UnitL]> {
+def V2Write_7c_1F_1L : SchedWriteRes<[V2UnitF, V2UnitL]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def V2Write_7cyc_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {
+def V2Write_7c_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def V2Write_1cyc_1L01_1D : SchedWriteRes<[V2UnitL01, V2UnitD]> {
+def V2Write_1c_1L01_1D : SchedWriteRes<[V2UnitL01, V2UnitD]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def V2Write_5cyc_1M0_1V : SchedWriteRes<[V2UnitM0, V2UnitV]> {
+def V2Write_5c_1M0_1V : SchedWriteRes<[V2UnitM0, V2UnitV]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def V2Write_2cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {
+def V2Write_2c_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def V2Write_2cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {
+def V2Write_2c_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def V2Write_2cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {
+def V2Write_2c_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {
+def V2Write_4c_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_4cyc_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {
+def V2Write_4c_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_4cyc_1V13_1V : SchedWriteRes<[V2UnitV13, V2UnitV]> {
+def V2Write_4c_1V13_1V : SchedWriteRes<[V2UnitV13, V2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {
+def V2Write_4c_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {
+def V2Write_4c_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {
+def V2Write_4c_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_6cyc_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {
+def V2Write_6c_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_6cyc_2L : SchedWriteRes<[V2UnitL, V2UnitL]> {
+def V2Write_6c_2L : SchedWriteRes<[V2UnitL, V2UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_8cyc_1L_1V : SchedWriteRes<[V2UnitL, V2UnitV]> {
+def V2Write_8c_1L_1V : SchedWriteRes<[V2UnitL, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def V2Write_4cyc_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {
+def V2Write_4c_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_3cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
+def V2Write_3c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def V2Write_4cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
+def V2Write_4c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_1cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
+def V2Write_1c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
let Latency = 1;
let NumMicroOps = 2;
}
-def V2Write_2cyc_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
+def V2Write_2c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def V2Write_6cyc_2V1 : SchedWriteRes<[V2UnitV1, V2UnitV1]> {
+def V2Write_6c_2V1 : SchedWriteRes<[V2UnitV1, V2UnitV1]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_4cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {
+def V2Write_4c_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_5cyc_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {
+def V2Write_5c_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def V2Write_5cyc_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {
+def V2Write_5c_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def V2Write_5cyc_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {
+def V2Write_5c_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1V1_1M0 : SchedWriteRes<[V2UnitV1, V2UnitM0]> {
+def V2Write_6c_1V1_1M0 : SchedWriteRes<[V2UnitV1, V2UnitM0]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_7cyc_1M0_1V02 : SchedWriteRes<[V2UnitM0, V2UnitV02]> {
+def V2Write_7c_1M0_1V02 : SchedWriteRes<[V2UnitM0, V2UnitV02]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def V2Write_2cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {
+def V2Write_2c_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def V2Write_3cyc_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {
+def V2Write_3c_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1V_1V13 : SchedWriteRes<[V2UnitV, V2UnitV13]> {
+def V2Write_6c_1V_1V13 : SchedWriteRes<[V2UnitV, V2UnitV13]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1L_1M : SchedWriteRes<[V2UnitL, V2UnitM]> {
+def V2Write_6c_1L_1M : SchedWriteRes<[V2UnitL, V2UnitM]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_6cyc_1L_1S : SchedWriteRes<[V2UnitL, V2UnitS]> {
+def V2Write_6c_1L_1S : SchedWriteRes<[V2UnitL, V2UnitS]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def V2Write_4cyc_2V13 : SchedWriteRes<[V2UnitV13, V2UnitV13]> {
+def V2Write_4c_2V13 : SchedWriteRes<[V2UnitV13, V2UnitV13]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def V2Write_8cyc_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> {
+def V2Write_8c_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> {
let Latency = 8;
let NumMicroOps = 2;
}
@@ -384,62 +384,62 @@ def V2Write_8cyc_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> {
//===----------------------------------------------------------------------===//
// Define generic 3 micro-op types
-def V2Write_1cyc_1L01_1D_1I : SchedWriteRes<[V2UnitL01, V2UnitD, V2UnitI]> {
+def V2Write_1c_1L01_1D_1I : SchedWriteRes<[V2UnitL01, V2UnitD, V2UnitI]> {
let Latency = 1;
let NumMicroOps = 3;
}
-def V2Write_2cyc_1L01_1V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitI]> {
+def V2Write_2c_1L01_1V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitI]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def V2Write_2cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {
+def V2Write_2c_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def V2Write_4cyc_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {
+def V2Write_4c_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 3;
}
-def V2Write_9cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {
+def V2Write_9c_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 3;
}
-def V2Write_4cyc_3V01 : SchedWriteRes<[V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_4c_3V01 : SchedWriteRes<[V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 3;
}
-def V2Write_7cyc_1M_1M0_1V : SchedWriteRes<[V2UnitM, V2UnitM0, V2UnitV]> {
+def V2Write_7c_1M_1M0_1V : SchedWriteRes<[V2UnitM, V2UnitM0, V2UnitV]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def V2Write_2cyc_1L01_1S_1V : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV]> {
+def V2Write_2c_1L01_1S_1V : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def V2Write_2cyc_1L01_1S_1V01 : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV01]> {
+def V2Write_2c_1L01_1S_1V01 : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def V2Write_6cyc_3L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL]> {
+def V2Write_6c_3L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL]> {
let Latency = 6;
let NumMicroOps = 3;
}
-def V2Write_6cyc_3V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_6c_3V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 6;
let NumMicroOps = 3;
}
-def V2Write_8cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {
+def V2Write_8c_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 3;
}
@@ -447,126 +447,126 @@ def V2Write_8cyc_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {
//===----------------------------------------------------------------------===//
// Define generic 4 micro-op types
-def V2Write_2cyc_1L01_2V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitI]> {
+def V2Write_2c_1L01_2V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitI]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def V2Write_2cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_2c_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def V2Write_4cyc_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_4c_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def V2Write_5cyc_1I_3L : SchedWriteRes<[V2UnitI, V2UnitL, V2UnitL, V2UnitL]> {
+def V2Write_5c_1I_3L : SchedWriteRes<[V2UnitI, V2UnitL, V2UnitL, V2UnitL]> {
let Latency = 5;
let NumMicroOps = 4;
}
-def V2Write_9cyc_2L_2V1 : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV1,
- V2UnitV1]> {
+def V2Write_9c_2L_2V1 : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV1,
+ V2UnitV1]> {
let Latency = 9;
let NumMicroOps = 4;
}
-def V2Write_6cyc_4V0 : SchedWriteRes<[V2UnitV0, V2UnitV0, V2UnitV0, V2UnitV0]> {
+def V2Write_6c_4V0 : SchedWriteRes<[V2UnitV0, V2UnitV0, V2UnitV0, V2UnitV0]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def V2Write_8cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_8c_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def V2Write_6cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
- V2UnitV13]> {
+def V2Write_6c_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
+ V2UnitV13]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def V2Write_8cyc_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
- V2UnitV13]> {
+def V2Write_8c_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
+ V2UnitV13]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def V2Write_6cyc_4V02 : SchedWriteRes<[V2UnitV02, V2UnitV02, V2UnitV02,
- V2UnitV02]> {
+def V2Write_6c_4V02 : SchedWriteRes<[V2UnitV02, V2UnitV02, V2UnitV02,
+ V2UnitV02]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def V2Write_6cyc_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_6c_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def V2Write_8cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {
+def V2Write_8c_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def V2Write_9cyc_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {
+def V2Write_9c_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 4;
}
-def V2Write_2cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,
- V2UnitV]> {
+def V2Write_2c_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,
+ V2UnitV]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def V2Write_4cyc_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,
- V2UnitV]> {
+def V2Write_4c_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,
+ V2UnitV]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def V2Write_8cyc_2M0_2V02 : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitV02,
- V2UnitV02]> {
+def V2Write_8c_2M0_2V02 : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitV02,
+ V2UnitV02]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def V2Write_8cyc_2V_2V1 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV1,
- V2UnitV1]> {
+def V2Write_8c_2V_2V1 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV1,
+ V2UnitV1]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def V2Write_4cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,
- V2UnitM]> {
+def V2Write_4c_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,
+ V2UnitM]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def V2Write_5cyc_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,
- V2UnitM]> {
+def V2Write_5c_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,
+ V2UnitM]> {
let Latency = 5;
let NumMicroOps = 4;
}
-def V2Write_6cyc_2I_2L : SchedWriteRes<[V2UnitI, V2UnitI, V2UnitL, V2UnitL]> {
+def V2Write_6c_2I_2L : SchedWriteRes<[V2UnitI, V2UnitI, V2UnitL, V2UnitL]> {
let Latency = 6;
let NumMicroOps = 4;
}
-def V2Write_7cyc_4L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL]> {
+def V2Write_7c_4L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL]> {
let Latency = 7;
let NumMicroOps = 4;
}
-def V2Write_6cyc_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitV01]> {
+def V2Write_6c_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitV01]> {
let Latency = 6;
let NumMicroOps = 4;
}
@@ -574,32 +574,32 @@ def V2Write_6cyc_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
//===----------------------------------------------------------------------===//
// Define generic 5 micro-op types
-def V2Write_2cyc_1L01_2V01_2I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitI, V2UnitI]> {
+def V2Write_2c_1L01_2V01_2I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitI, V2UnitI]> {
let Latency = 2;
let NumMicroOps = 5;
}
-def V2Write_8cyc_2L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_8c_2L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 8;
let NumMicroOps = 5;
}
-def V2Write_9cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_9c_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 9;
let NumMicroOps = 5;
}
-def V2Write_10cyc_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_10c_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 10;
let NumMicroOps = 5;
}
-def V2Write_6cyc_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_6c_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 6;
let NumMicroOps = 5;
}
@@ -607,62 +607,62 @@ def V2Write_6cyc_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV,
//===----------------------------------------------------------------------===//
// Define generic 6 micro-op types
-def V2Write_8cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_8c_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 6;
}
-def V2Write_9cyc_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_9c_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 6;
}
-def V2Write_9cyc_2L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_9c_2L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 6;
}
-def V2Write_9cyc_2L_2V_2S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,
- V2UnitV, V2UnitS, V2UnitS]> {
+def V2Write_9c_2L_2V_2S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,
+ V2UnitV, V2UnitS, V2UnitS]> {
let Latency = 9;
let NumMicroOps = 6;
}
-def V2Write_9cyc_2V_4V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
- V2UnitV13, V2UnitV13, V2UnitV13]> {
+def V2Write_9c_2V_4V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,
+ V2UnitV13, V2UnitV13, V2UnitV13]> {
let Latency = 9;
let NumMicroOps = 6;
}
-def V2Write_2cyc_3L01_3V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_2c_3L01_3V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 2;
let NumMicroOps = 6;
}
-def V2Write_4cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_4c_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 6;
}
-def V2Write_5cyc_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_5c_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 5;
let NumMicroOps = 6;
}
-def V2Write_2cyc_3L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_2c_3L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 6;
}
-def V2Write_4cyc_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS,
- V2UnitS, V2UnitV01, V2UnitV01]> {
+def V2Write_4c_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS,
+ V2UnitS, V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 6;
}
@@ -670,8 +670,8 @@ def V2Write_4cyc_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS,
//===----------------------------------------------------------------------===//
// Define generic 7 micro-op types
-def V2Write_8cyc_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_8c_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 7;
}
@@ -679,36 +679,36 @@ def V2Write_8cyc_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 8 micro-op types
-def V2Write_2cyc_4L01_4V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_2c_4L01_4V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 2;
let NumMicroOps = 8;
}
-def V2Write_2cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_2c_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 2;
let NumMicroOps = 8;
}
-def V2Write_4cyc_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_4c_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 4;
let NumMicroOps = 8;
}
-def V2Write_6cyc_2L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_6c_2L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 6;
let NumMicroOps = 8;
}
-def V2Write_8cyc_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
- V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_8c_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
+ V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 8;
let NumMicroOps = 8;
}
@@ -716,23 +716,23 @@ def V2Write_8cyc_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 9 micro-op types
-def V2Write_6cyc_3L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_6c_3L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 6;
let NumMicroOps = 9;
}
-def V2Write_10cyc_1L_8V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV, V2UnitV,
- V2UnitV]> {
+def V2Write_10c_1L_8V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV]> {
let Latency = 10;
let NumMicroOps = 9;
}
-def V2Write_10cyc_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV,
- V2UnitL, V2UnitL, V2UnitL,
- V2UnitS, V2UnitS, V2UnitS]> {
+def V2Write_10c_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV,
+ V2UnitL, V2UnitL, V2UnitL,
+ V2UnitS, V2UnitS, V2UnitS]> {
let Latency = 10;
let NumMicroOps = 9;
}
@@ -740,9 +740,9 @@ def V2Write_10cyc_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV,
//===----------------------------------------------------------------------===//
// Define generic 10 micro-op types
-def V2Write_9cyc_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
- V2UnitL, V2UnitL, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV]> {
+def V2Write_9c_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
+ V2UnitL, V2UnitL, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 10;
}
@@ -750,26 +750,26 @@ def V2Write_9cyc_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 12 micro-op types
-def V2Write_5cyc_4L01_8V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_5c_4L01_8V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 5;
let NumMicroOps = 12;
}
-def V2Write_9cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitL, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_9c_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitL, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 9;
let NumMicroOps = 12;
}
-def V2Write_10cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitL, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV]> {
+def V2Write_10c_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitL, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV]> {
let Latency = 10;
let NumMicroOps = 12;
}
@@ -777,22 +777,22 @@ def V2Write_10cyc_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 16 micro-op types
-def V2Write_7cyc_4L01_12V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01]> {
+def V2Write_7c_4L01_12V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01]> {
let Latency = 7;
let NumMicroOps = 16;
}
-def V2Write_10cyc_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
- V2UnitL, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV,
- V2UnitV, V2UnitV, V2UnitV,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS]> {
+def V2Write_10c_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
+ V2UnitL, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV,
+ V2UnitV, V2UnitV, V2UnitV,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS]> {
let Latency = 10;
let NumMicroOps = 16;
}
@@ -800,12 +800,12 @@ def V2Write_10cyc_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,
//===----------------------------------------------------------------------===//
// Define generic 18 micro-op types
-def V2Write_7cyc_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01]> {
+def V2Write_7c_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01]> {
let Latency = 7;
let NumMicroOps = 18;
}
@@ -813,16 +813,16 @@ def V2Write_7cyc_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 27 micro-op types
-def V2Write_7cyc_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01]> {
+def V2Write_7c_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01]> {
let Latency = 7;
let NumMicroOps = 27;
}
@@ -830,19 +830,19 @@ def V2Write_7cyc_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 36 micro-op types
-def V2Write_11cyc_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01, V2UnitL01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01]> {
+def V2Write_11c_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01, V2UnitL01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01]> {
let Latency = 11;
let NumMicroOps = 36;
}
@@ -850,30 +850,30 @@ def V2Write_11cyc_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,
//===----------------------------------------------------------------------===//
// Define generic 54 micro-op types
-def V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitL01, V2UnitL01,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitS, V2UnitS, V2UnitS,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01,
- V2UnitV01, V2UnitV01]> {
+def V2Write_11c_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitL01, V2UnitL01,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitS, V2UnitS, V2UnitS,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01,
+ V2UnitV01, V2UnitV01]> {
let Latency = 11;
let NumMicroOps = 54;
}
@@ -882,80 +882,80 @@ def V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
// Define predicate-controlled types
def V2Write_ArithI : SchedWriteVariant<[
- SchedVar<IsCheapLSL, [V2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [V2Write_1c_1I]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;
def V2Write_ArithF : SchedWriteVariant<[
- SchedVar<IsCheapLSL, [V2Write_1cyc_1F]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<IsCheapLSL, [V2Write_1c_1F]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;
def V2Write_Logical : SchedWriteVariant<[
- SchedVar<NeoverseNoLSL, [V2Write_1cyc_1F]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<NeoverseNoLSL, [V2Write_1c_1F]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;
def V2Write_Extr : SchedWriteVariant<[
- SchedVar<IsRORImmIdiomPred, [V2Write_1cyc_1I]>,
- SchedVar<NoSchedPred, [V2Write_3cyc_1I_1M]>]>;
+ SchedVar<IsRORImmIdiomPred, [V2Write_1c_1I]>,
+ SchedVar<NoSchedPred, [V2Write_3c_1I_1M]>]>;
def V2Write_LdrHQ : SchedWriteVariant<[
- SchedVar<NeoverseHQForm, [V2Write_7cyc_1I_1L]>,
- SchedVar<NoSchedPred, [V2Write_6cyc_1L]>]>;
+ SchedVar<NeoverseHQForm, [V2Write_7c_1I_1L]>,
+ SchedVar<NoSchedPred, [V2Write_6c_1L]>]>;
def V2Write_StrHQ : SchedWriteVariant<[
- SchedVar<NeoverseHQForm, [V2Write_2cyc_1L01_1V01_1I]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1L01_1V01]>]>;
+ SchedVar<NeoverseHQForm, [V2Write_2c_1L01_1V01_1I]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1L01_1V01]>]>;
-def V2Write_0or1cyc_1I : SchedWriteVariant<[
- SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
- SchedVar<NoSchedPred, [V2Write_1cyc_1I]>]>;
+def V2Write_0or1c_1I : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V2Write_0c]>,
+ SchedVar<NoSchedPred, [V2Write_1c_1I]>]>;
-def V2Write_0or2cyc_1V : SchedWriteVariant<[
- SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1V]>]>;
+def V2Write_0or2c_1V : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V2Write_0c]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1V]>]>;
-def V2Write_0or3cyc_1M0 : SchedWriteVariant<[
- SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
- SchedVar<NoSchedPred, [V2Write_3cyc_1M0]>]>;
+def V2Write_0or3c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoverseZeroMove, [V2Write_0c]>,
+ SchedVar<NoSchedPred, [V2Write_3c_1M0]>]>;
-def V2Write_2or3cyc_1M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_3cyc_1M]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+def V2Write_2or3c_1M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_3c_1M]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;
-def V2Write_3or4cyc_2M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_4cyc_2M]>,
- SchedVar<NoSchedPred, [V2Write_3cyc_2M]>]>;
+def V2Write_3or4c_2M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_4c_2M]>,
+ SchedVar<NoSchedPred, [V2Write_3c_2M]>]>;
-def V2Write_1or2cyc_1M0 : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_2cyc_1M0]>,
- SchedVar<NoSchedPred, [V2Write_1cyc_1M0]>]>;
+def V2Write_1or2c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_2c_1M0]>,
+ SchedVar<NoSchedPred, [V2Write_1c_1M0]>]>;
-def V2Write_2or3cyc_1M0 : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_3cyc_1M0]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M0]>]>;
+def V2Write_2or3c_1M0 : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_3c_1M0]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M0]>]>;
-def V2Write_1or2cyc_1M0_1M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_2cyc_1M0_1M]>,
- SchedVar<NoSchedPred, [V2Write_1cyc_1M0_1M]>]>;
+def V2Write_1or2c_1M0_1M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_2c_1M0_1M]>,
+ SchedVar<NoSchedPred, [V2Write_1c_1M0_1M]>]>;
-def V2Write_3or4cyc_1M0_1M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_4cyc_1M0_1M]>,
- SchedVar<NoSchedPred, [V2Write_3cyc_1M0_1M]>]>;
+def V2Write_3or4c_1M0_1M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_4c_1M0_1M]>,
+ SchedVar<NoSchedPred, [V2Write_3c_1M0_1M]>]>;
-def V2Write_4or5cyc_2M0_2M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_5cyc_2M0_2M]>,
- SchedVar<NoSchedPred, [V2Write_4cyc_2M0_2M]>]>;
+def V2Write_4or5c_2M0_2M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_5c_2M0_2M]>,
+ SchedVar<NoSchedPred, [V2Write_4c_2M0_2M]>]>;
-def V2Write_4or5cyc_1V0_1M0 : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_5cyc_1V0_1M0]>,
- SchedVar<NoSchedPred, [V2Write_4cyc_1V0_1M0]>]>;
+def V2Write_4or5c_1V0_1M0 : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_5c_1V0_1M0]>,
+ SchedVar<NoSchedPred, [V2Write_4c_1V0_1M0]>]>;
-def V2Write_2or3cyc_1V0_1M : SchedWriteVariant<[
- SchedVar<NeoversePdIsPg, [V2Write_3cyc_1V0_1M]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1V0_1M]>]>;
+def V2Write_2or3c_1V0_1M : SchedWriteVariant<[
+ SchedVar<NeoversePdIsPg, [V2Write_3c_1V0_1M]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1V0_1M]>]>;
def V2Write_IncDec : SchedWriteVariant<[
- SchedVar<NeoverseCheapIncDec, [V2Write_1cyc_1F]>,
- SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
+ SchedVar<NeoverseCheapIncDec, [V2Write_1c_1F]>,
+ SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;
//===----------------------------------------------------------------------===//
// Define forwarded types
@@ -1071,17 +1071,17 @@ def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;
//===----------------------------------------------------------------------===//
// Define types with long resource cycles (rc)
-def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }
-def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }
-def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
-def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
-def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
-def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
-def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
-def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
-def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
-def V2Write_16cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [14]; }
-def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
+def V2Write_6c_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }
+def V2Write_7c_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }
+def V2Write_10c_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
+def V2Write_10c_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
+def V2Write_10c_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
+def V2Write_10c_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
+def V2Write_13c_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
+def V2Write_13c_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
+def V2Write_15c_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
+def V2Write_16c_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [14]; }
+def V2Write_16c_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
// Miscellaneous
// -----------------------------------------------------------------------------
@@ -1093,31 +1093,31 @@ def : InstRW<[WriteI], (instrs COPY)>;
// Branch, immed
// Compare and branch
-def : SchedAlias<WriteBr, V2Write_1cyc_1B>;
+def : SchedAlias<WriteBr, V2Write_1c_1B>;
// Branch, register
-def : SchedAlias<WriteBrReg, V2Write_1cyc_1B>;
+def : SchedAlias<WriteBrReg, V2Write_1c_1B>;
// Branch and link, immed
// Branch and link, register
-def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
+def : InstRW<[V2Write_1c_1B_1R], (instrs BL, BLR)>;
// §3.4 Arithmetic and Logical Instructions
// -----------------------------------------------------------------------------
// ALU, basic
// ALU, basic, flagset
-def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
+def : SchedAlias<WriteI, V2Write_1c_1I>;
+def : InstRW<[V2Write_1c_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
"^(ADC|SBC)S[WX]r$",
"^ANDS[WX]ri$")>;
-def : InstRW<[V2Write_0or1cyc_1I], (instregex "^MOVZ[WX]i$")>;
+def : InstRW<[V2Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;
// ALU, extend and shift
-def : SchedAlias<WriteIEReg, V2Write_2cyc_1M>;
+def : SchedAlias<WriteIEReg, V2Write_2c_1M>;
// Conditional compare
-def : InstRW<[V2Write_1cyc_1F], (instregex "^CCM[NP][WX][ir]")>;
+def : InstRW<[V2Write_1c_1F], (instregex "^CCM[NP][WX][ir]")>;
// Arithmetic, LSL shift, shift <= 4
// Arithmetic, flagset, LSL shift, shift <= 4
@@ -1127,23 +1127,23 @@ def : InstRW<[V2Write_ArithF],
(instregex "^(ADD|SUB)S[WX]rs$")>;
// Arithmetic, immediate to logical address tag
-def : InstRW<[V2Write_2cyc_1M], (instrs ADDG, SUBG)>;
+def : InstRW<[V2Write_2c_1M], (instrs ADDG, SUBG)>;
// Convert floating-point condition flags
// Flag manipulation instructions
def : WriteRes<WriteSys, []> { let Latency = 1; }
// Insert Random Tags
-def : InstRW<[V2Write_2cyc_1M], (instrs IRG, IRGstack)>;
+def : InstRW<[V2Write_2c_1M], (instrs IRG, IRGstack)>;
// Insert Tag Mask
// Subtract Pointer
// Subtract Pointer, flagset
-def : InstRW<[V2Write_1cyc_1I], (instrs GMI, SUBP, SUBPS)>;
+def : InstRW<[V2Write_1c_1I], (instrs GMI, SUBP, SUBPS)>;
// Logical, shift, no flagset
-def : InstRW<[V2Write_1cyc_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
-def : InstRW<[V2Write_0or1cyc_1I], (instregex "^ORR[WX]rs$")>;
+def : InstRW<[V2Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
+def : InstRW<[V2Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;
// Logical, shift, flagset
def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
@@ -1151,17 +1151,17 @@ def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
// Move and shift instructions
// -----------------------------------------------------------------------------
-def : SchedAlias<WriteImm, V2Write_1cyc_1I>;
+def : SchedAlias<WriteImm, V2Write_1c_1I>;
// §3.5 Divide and multiply instructions
// -----------------------------------------------------------------------------
// SDIV, UDIV
-def : SchedAlias<WriteID32, V2Write_12cyc_1M0>;
-def : SchedAlias<WriteID64, V2Write_20cyc_1M0>;
+def : SchedAlias<WriteID32, V2Write_12c_1M0>;
+def : SchedAlias<WriteID64, V2Write_20c_1M0>;
-def : SchedAlias<WriteIM32, V2Write_2cyc_1M>;
-def : SchedAlias<WriteIM64, V2Write_2cyc_1M>;
+def : SchedAlias<WriteIM32, V2Write_2c_1M>;
+def : SchedAlias<WriteIM64, V2Write_2c_1M>;
// Multiply
// Multiply accumulate, W-form
@@ -1175,7 +1175,7 @@ def : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA],
(instregex "^(S|U)M(ADD|SUB)Lrrr$")>;
// Multiply high
-def : InstRW<[V2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>;
+def : InstRW<[V2Write_3c_1M], (instrs SMULHrr, UMULHrr)>;
// Pointer Authentication Instructions (v8.3 PAC)
// -----------------------------------------------------------------------------
@@ -1185,27 +1185,27 @@ def : InstRW<[V2Write_3cyc_1M], (instrs SMULHrr, UMULHrr)>;
// Compute pointer authentication code for data address
// Compute pointer authentication code, using generic key
// Compute pointer authentication code for instruction address
-def : InstRW<[V2Write_5cyc_1M0], (instregex "^AUT", "^PAC")>;
+def : InstRW<[V2Write_5c_1M0], (instregex "^AUT", "^PAC")>;
// Branch and link, register, with pointer authentication
// Branch, register, with pointer authentication
// Branch, return, with pointer authentication
-def : InstRW<[V2Write_6cyc_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,
+def : InstRW<[V2Write_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,
BRAAZ, BRAB, BRABZ, RETAA, RETAB,
ERETAA, ERETAB)>;
// Load register, with pointer authentication
-def : InstRW<[V2Write_9cyc_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
+def : InstRW<[V2Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
// Strip pointer authentication code
-def : InstRW<[V2Write_2cyc_1M0], (instrs XPACD, XPACI, XPACLRI)>;
+def : InstRW<[V2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
// Miscellaneous data-processing instructions
// -----------------------------------------------------------------------------
// Address generation
-def : InstRW<[V2Write_1cyc_1F], (instrs ADR, ADRP)>;
+def : InstRW<[V2Write_1c_1F], (instrs ADR, ADRP)>;
// Bitfield extract, one reg
// Bitfield extract, two regs
@@ -1213,27 +1213,27 @@ def : SchedAlias<WriteExtr, V2Write_Extr>;
def : InstRW<[V2Write_Extr], (instrs EXTRWrri, EXTRXrri)>;
// Bitfield move, basic
-def : SchedAlias<WriteIS, V2Write_1cyc_1I>;
+def : SchedAlias<WriteIS, V2Write_1c_1I>;
// Bitfield move, insert
-def : InstRW<[V2Write_2cyc_1M], (instregex "^BFM[WX]ri$")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^BFM[WX]ri$")>;
// Load instructions
// -----------------------------------------------------------------------------
// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3.
-def : SchedAlias<WriteLD, V2Write_4cyc_1L>;
-def : SchedAlias<WriteLDIdx, V2Write_4cyc_1L>;
+def : SchedAlias<WriteLD, V2Write_4c_1L>;
+def : SchedAlias<WriteLDIdx, V2Write_4c_1L>;
// Load register, literal
-def : InstRW<[V2Write_5cyc_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;
+def : InstRW<[V2Write_5c_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;
// Load pair, signed immed offset, signed words
-def : InstRW<[V2Write_5cyc_1I_3L, WriteLDHi], (instrs LDPSWi)>;
+def : InstRW<[V2Write_5c_1I_3L, WriteLDHi], (instrs LDPSWi)>;
// Load pair, immed post-index or immed pre-index, signed words
-def : InstRW<[WriteAdr, V2Write_5cyc_1I_3L, WriteLDHi],
+def : InstRW<[WriteAdr, V2Write_5c_1I_3L, WriteLDHi],
(instregex "^LDPSW(post|pre)$")>;
// Store instructions
@@ -1241,17 +1241,17 @@ def : InstRW<[WriteAdr, V2Write_5cyc_1I_3L, WriteLDHi],
// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I.
-def : SchedAlias<WriteST, V2Write_1cyc_1L01_1D>;
-def : SchedAlias<WriteSTIdx, V2Write_1cyc_1L01_1D>;
-def : SchedAlias<WriteSTP, V2Write_1cyc_1L01_1D>;
-def : SchedAlias<WriteAdr, V2Write_1cyc_1I>;
+def : SchedAlias<WriteST, V2Write_1c_1L01_1D>;
+def : SchedAlias<WriteSTIdx, V2Write_1c_1L01_1D>;
+def : SchedAlias<WriteSTP, V2Write_1c_1L01_1D>;
+def : SchedAlias<WriteAdr, V2Write_1c_1I>;
// Tag load instructions
// -----------------------------------------------------------------------------
// Load allocation tag
// Load multiple allocation tags
-def : InstRW<[V2Write_4cyc_1L], (instrs LDG, LDGM)>;
+def : InstRW<[V2Write_4c_1L], (instrs LDG, LDGM)>;
// Tag store instructions
// -----------------------------------------------------------------------------
@@ -1262,7 +1262,7 @@ def : InstRW<[V2Write_4cyc_1L], (instrs LDG, LDGM)>;
// Store Allocation Tag to one or two granules, zeroing, pre-index
// Store allocation tag and reg pair to memory, post-Index
// Store allocation tag and reg pair to memory, pre-Index
-def : InstRW<[V2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
+def : InstRW<[V2Write_1c_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
ST2GPreIndex, ST2GPostIndex,
STZGPreIndex, STZGPostIndex,
STZ2GPreIndex, STZ2GPostIndex,
@@ -1272,7 +1272,7 @@ def : InstRW<[V2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
// Store allocation tag to two granules, zeroing, signed offset
// Store allocation tag and reg pair to memory, signed offset
// Store multiple allocation tags
-def : InstRW<[V2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi,
+def : InstRW<[V2Write_1c_1L01_1D], (instrs STGi, ST2Gi, STZGi,
STZ2Gi, STGPi, STGM, STZGM)>;
// FP data processing instructions
@@ -1283,27 +1283,27 @@ def : InstRW<[V2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi,
// FP min/max
// FP negate
// FP select
-def : SchedAlias<WriteF, V2Write_2cyc_1V>;
+def : SchedAlias<WriteF, V2Write_2c_1V>;
// FP compare
-def : SchedAlias<WriteFCmp, V2Write_2cyc_1V0>;
+def : SchedAlias<WriteFCmp, V2Write_2c_1V0>;
// FP divide, square root
-def : SchedAlias<WriteFDiv, V2Write_7cyc_1V02>;
+def : SchedAlias<WriteFDiv, V2Write_7c_1V02>;
// FP divide, H-form
-def : InstRW<[V2Write_7cyc_1V02], (instrs FDIVHrr)>;
+def : InstRW<[V2Write_7c_1V02], (instrs FDIVHrr)>;
// FP divide, S-form
-def : InstRW<[V2Write_10cyc_1V02], (instrs FDIVSrr)>;
+def : InstRW<[V2Write_10c_1V02], (instrs FDIVSrr)>;
// FP divide, D-form
-def : InstRW<[V2Write_15cyc_1V02], (instrs FDIVDrr)>;
+def : InstRW<[V2Write_15c_1V02], (instrs FDIVDrr)>;
// FP square root, H-form
-def : InstRW<[V2Write_7cyc_1V02], (instrs FSQRTHr)>;
+def : InstRW<[V2Write_7c_1V02], (instrs FSQRTHr)>;
// FP square root, S-form
-def : InstRW<[V2Write_9cyc_1V02], (instrs FSQRTSr)>;
+def : InstRW<[V2Write_9c_1V02], (instrs FSQRTSr)>;
// FP square root, D-form
-def : InstRW<[V2Write_16cyc_1V02], (instrs FSQRTDr)>;
+def : InstRW<[V2Write_16c_1V02], (instrs FSQRTDr)>;
// FP multiply
def : WriteRes<WriteFMul, [V2UnitV]> { let Latency = 3; }
@@ -1313,56 +1313,56 @@ def : InstRW<[V2Wr_FMA, ReadDefault, ReadDefault, V2Rd_FMA],
(instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
// FP round to integral
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",
+def : InstRW<[V2Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",
"^FRINT(32|64)[XZ][SD]r$")>;
// FP miscellaneous instructions
// -----------------------------------------------------------------------------
// FP convert, from gen to vec reg
-def : InstRW<[V2Write_3cyc_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
+def : InstRW<[V2Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
// FP convert, from vec to gen reg
-def : InstRW<[V2Write_3cyc_1V01],
+def : InstRW<[V2Write_3c_1V01],
(instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;
// FP convert, Javascript from vec to gen reg
-def : SchedAlias<WriteFCvt, V2Write_3cyc_1V0>;
+def : SchedAlias<WriteFCvt, V2Write_3c_1V0>;
// FP convert, from vec to vec reg
-def : InstRW<[V2Write_3cyc_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,
+def : InstRW<[V2Write_3c_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,
FCVTHDr, FCVTSDr, FCVTXNv1i64)>;
// FP move, immed
// FP move, register
-def : SchedAlias<WriteFImm, V2Write_2cyc_1V>;
+def : SchedAlias<WriteFImm, V2Write_2c_1V>;
// FP transfer, from gen to low half of vec reg
-def : InstRW<[V2Write_0or3cyc_1M0],
+def : InstRW<[V2Write_0or3c_1M0],
(instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
// FP transfer, from gen to high half of vec reg
-def : InstRW<[V2Write_5cyc_1M0_1V], (instrs FMOVXDHighr)>;
+def : InstRW<[V2Write_5c_1M0_1V], (instrs FMOVXDHighr)>;
// FP transfer, from vec to gen reg
-def : SchedAlias<WriteFCopy, V2Write_2cyc_2V01>;
+def : SchedAlias<WriteFCopy, V2Write_2c_2V01>;
// FP load instructions
// -----------------------------------------------------------------------------
// Load vector reg, literal, S/D/Q forms
-def : InstRW<[V2Write_7cyc_1F_1L], (instregex "^LDR[SDQ]l$")>;
+def : InstRW<[V2Write_7c_1F_1L], (instregex "^LDR[SDQ]l$")>;
// Load vector reg, unscaled immed
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LDUR[BHSDQ]i$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LDUR[BHSDQ]i$")>;
// Load vector reg, immed post-index
// Load vector reg, immed pre-index
-def : InstRW<[WriteAdr, V2Write_6cyc_1I_1L],
+def : InstRW<[WriteAdr, V2Write_6c_1I_1L],
(instregex "^LDR[BHSDQ](pre|post)$")>;
// Load vector reg, unsigned immed
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;
// Load vector reg, register offset, basic
// Load vector reg, register offset, scale, S/D-form
@@ -1373,19 +1373,19 @@ def : InstRW<[V2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
def : InstRW<[V2Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;
// Load vector pair, immed offset, S/D-form
-def : InstRW<[V2Write_6cyc_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;
+def : InstRW<[V2Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;
// Load vector pair, immed offset, Q-form
-def : InstRW<[V2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
+def : InstRW<[V2Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
// Load vector pair, immed post-index, S/D-form
// Load vector pair, immed pre-index, S/D-form
-def : InstRW<[WriteAdr, V2Write_6cyc_1I_1L, WriteLDHi],
+def : InstRW<[WriteAdr, V2Write_6c_1I_1L, WriteLDHi],
(instregex "^LDP[SD](pre|post)$")>;
// Load vector pair, immed post-index, Q-form
// Load vector pair, immed pre-index, Q-form
-def : InstRW<[WriteAdr, V2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
+def : InstRW<[WriteAdr, V2Write_6c_2I_2L, WriteLDHi], (instrs LDPQpost,
LDPQpre)>;
// FP store instructions
@@ -1393,18 +1393,18 @@ def : InstRW<[WriteAdr, V2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
// Store vector reg, unscaled immed, B/H/S/D-form
// Store vector reg, unscaled immed, Q-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>;
// Store vector reg, immed post-index, B/H/S/D-form
// Store vector reg, immed post-index, Q-form
// Store vector reg, immed pre-index, B/H/S/D-form
// Store vector reg, immed pre-index, Q-form
-def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I],
+def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01_1I],
(instregex "^STR[BHSDQ](pre|post)$")>;
// Store vector reg, unsigned immed, B/H/S/D-form
// Store vector reg, unsigned immed, Q-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>;
// Store vector reg, register offset, basic, B/H/S/D-form
// Store vector reg, register offset, basic, Q-form
@@ -1421,23 +1421,23 @@ def : InstRW<[V2Write_StrHQ, ReadAdrBase],
// Store vector pair, immed offset, S-form
// Store vector pair, immed offset, D-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^STN?P[SD]i$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STN?P[SD]i$")>;
// Store vector pair, immed offset, Q-form
-def : InstRW<[V2Write_2cyc_1L01_2V01], (instrs STPQi, STNPQi)>;
+def : InstRW<[V2Write_2c_1L01_2V01], (instrs STPQi, STNPQi)>;
// Store vector pair, immed post-index, S-form
// Store vector pair, immed post-index, D-form
// Store vector pair, immed pre-index, S-form
// Store vector pair, immed pre-index, D-form
-def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01_1I],
+def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01_1I],
(instregex "^STP[SD](pre|post)$")>;
// Store vector pair, immed post-index, Q-form
-def : InstRW<[V2Write_2cyc_1L01_2V01_1I], (instrs STPQpost)>;
+def : InstRW<[V2Write_2c_1L01_2V01_1I], (instrs STPQpost)>;
// Store vector pair, immed pre-index, Q-form
-def : InstRW<[V2Write_2cyc_1L01_2V01_2I], (instrs STPQpre)>;
+def : InstRW<[V2Write_2c_1L01_2V01_2I], (instrs STPQpre)>;
// ASIMD integer instructions
// -----------------------------------------------------------------------------
@@ -1450,22 +1450,22 @@ def : InstRW<[V2Write_2cyc_1L01_2V01_2I], (instrs STPQpre)>;
// ASIMD compare
// ASIMD logical
// ASIMD max/min, basic and pair-wise
-def : SchedAlias<WriteVd, V2Write_2cyc_1V>;
-def : SchedAlias<WriteVq, V2Write_2cyc_1V>;
+def : SchedAlias<WriteVd, V2Write_2c_1V>;
+def : SchedAlias<WriteVq, V2Write_2c_1V>;
// ASIMD absolute
diff accum
// ASIMD absolute
diff accum long
def : InstRW<[V2Wr_VA, V2Rd_VA], (instregex "^[SU]ABAL?v")>;
// ASIMD arith, reduce, 4H/4S
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;
// ASIMD arith, reduce, 8B/8H
-def : InstRW<[V2Write_4cyc_1V13_1V],
+def : InstRW<[V2Write_4c_1V13_1V],
(instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;
// ASIMD arith, reduce, 16B
-def : InstRW<[V2Write_4cyc_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;
+def : InstRW<[V2Write_4c_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;
// ASIMD dot product
// ASIMD dot product using signed and unsigned integers
@@ -1476,18 +1476,18 @@ def : InstRW<[V2Wr_VDOT, V2Rd_VDOT],
def : InstRW<[V2Wr_VMMA, V2Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;
// ASIMD max/min, reduce, 4H/4S
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$",
- "^[SU](MAX|MIN)Vv4i32v$")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$",
+ "^[SU](MAX|MIN)Vv4i32v$")>;
// ASIMD max/min, reduce, 8B/8H
-def : InstRW<[V2Write_4cyc_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",
- "^[SU](MAX|MIN)Vv8i16v$")>;
+def : InstRW<[V2Write_4c_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",
+ "^[SU](MAX|MIN)Vv8i16v$")>;
// ASIMD max/min, reduce, 16B
-def : InstRW<[V2Write_4cyc_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>;
+def : InstRW<[V2Write_4c_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>;
// ASIMD multiply
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>;
// ASIMD multiply accumulate
def : InstRW<[V2Wr_VMA, V2Rd_VMA], (instregex "^MLAv", "^MLSv")>;
@@ -1499,14 +1499,14 @@ def : InstRW<[V2Wr_VMAH, V2Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;
def : InstRW<[V2Wr_VMAL, V2Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;
// ASIMD multiply accumulate saturating long
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDML[AS]L[iv]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^SQDML[AS]L[iv]")>;
// ASIMD multiply/multiply long (8x8) polynomial, D-form
// ASIMD multiply/multiply long (8x8) polynomial, Q-form
-def : InstRW<[V2Write_3cyc_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>;
+def : InstRW<[V2Write_3c_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>;
// ASIMD multiply long
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;
// ASIMD pairwise add and accumulate long
def : InstRW<[V2Wr_VPA, V2Rd_VPA], (instregex "^[SU]ADALPv")>;
@@ -1515,25 +1515,25 @@ def : InstRW<[V2Wr_VPA, V2Rd_VPA], (instregex "^[SU]ADALPv")>;
def : InstRW<[V2Wr_VSA, V2Rd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>;
// ASIMD shift by immed, basic
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",
- "^SSHLLv", "^SSHR[dv]", "^USHLLv",
- "^USHR[dv]")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",
+ "^SSHLLv", "^SSHR[dv]", "^USHLLv",
+ "^USHR[dv]")>;
// ASIMD shift by immed and insert, basic
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>;
// ASIMD shift by immed, complex
-def : InstRW<[V2Write_4cyc_1V13],
+def : InstRW<[V2Write_4c_1V13],
(instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$",
"^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",
"^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]",
"^UQSHRN[bhsv]", "^URSHR[dv]")>;
// ASIMD shift by register, basic
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]SHLv")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^[SU]SHLv")>;
// ASIMD shift by register, complex
-def : InstRW<[V2Write_4cyc_1V13],
+def : InstRW<[V2Write_4c_1V13],
(instregex "^[SU]RSHLv", "^[SU]QRSHLv",
"^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;
@@ -1553,62 +1553,62 @@ def : InstRW<[V2Write_4cyc_1V13],
def : InstRW<[V2Wr_VFCMA, V2Rd_VFCMA], (instregex "^FCMLAv")>;
// ASIMD FP convert, long (F16 to F32)
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTL(v4|v8)i16")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTL(v4|v8)i16")>;
// ASIMD FP convert, long (F32 to F64)
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTL(v2|v4)i32")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FCVTL(v2|v4)i32")>;
// ASIMD FP convert, narrow (F32 to F16)
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTN(v4|v8)i16")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTN(v4|v8)i16")>;
// ASIMD FP convert, narrow (F64 to F32)
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVTN(v2|v4)i32",
+def : InstRW<[V2Write_3c_1V02], (instregex "^FCVTN(v2|v4)i32",
"^FCVTXN(v2|v4)f32")>;
// ASIMD FP convert, other, D-form F32 and Q-form F64
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
- "^FCVT[AMNPZ][SU]v1i64$",
- "^FCVTZ[SU]d$",
- "^[SU]CVTFv2f(32|64)$",
- "^[SU]CVTFv1i64$",
- "^[SU]CVTFd$")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
+ "^FCVT[AMNPZ][SU]v1i64$",
+ "^FCVTZ[SU]d$",
+ "^[SU]CVTFv2f(32|64)$",
+ "^[SU]CVTFv1i64$",
+ "^[SU]CVTFd$")>;
// ASIMD FP convert, other, D-form F16 and Q-form F32
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
- "^FCVT[AMNPZ][SU]v1i32$",
- "^FCVTZ[SU]s$",
- "^[SU]CVTFv4f(16|32)$",
- "^[SU]CVTFv1i32$",
- "^[SU]CVTFs$")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
+ "^FCVT[AMNPZ][SU]v1i32$",
+ "^FCVTZ[SU]s$",
+ "^[SU]CVTFv4f(16|32)$",
+ "^[SU]CVTFv1i32$",
+ "^[SU]CVTFs$")>;
// ASIMD FP convert, other, Q-form F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
- "^FCVT[AMNPZ][SU]v1f16$",
- "^FCVTZ[SU]h$",
- "^[SU]CVTFv8f16$",
- "^[SU]CVTFv1i16$",
- "^[SU]CVTFh$")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
+ "^FCVT[AMNPZ][SU]v1f16$",
+ "^FCVTZ[SU]h$",
+ "^[SU]CVTFv8f16$",
+ "^[SU]CVTFv1i16$",
+ "^[SU]CVTFh$")>;
// ASIMD FP divide, D-form, F16
-def : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FDIVv4f16)>;
+def : InstRW<[V2Write_7c_1V02_7rc], (instrs FDIVv4f16)>;
// ASIMD FP divide, D-form, F32
-def : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FDIVv2f32)>;
+def : InstRW<[V2Write_10c_1V02_5rc], (instrs FDIVv2f32)>;
// ASIMD FP divide, Q-form, F16
-def : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FDIVv8f16)>;
+def : InstRW<[V2Write_13c_1V02_13rc], (instrs FDIVv8f16)>;
// ASIMD FP divide, Q-form, F32
-def : InstRW<[V2Write_10cyc_1V02_10rc], (instrs FDIVv4f32)>;
+def : InstRW<[V2Write_10c_1V02_10rc], (instrs FDIVv4f32)>;
// ASIMD FP divide, Q-form, F64
-def : InstRW<[V2Write_15cyc_1V02_14rc], (instrs FDIVv2f64)>;
+def : InstRW<[V2Write_15c_1V02_14rc], (instrs FDIVv2f64)>;
// ASIMD FP max/min, reduce, F32 and D-form F16
-def : InstRW<[V2Write_4cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
+def : InstRW<[V2Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
// ASIMD FP max/min, reduce, Q-form F16
-def : InstRW<[V2Write_6cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
+def : InstRW<[V2Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
// ASIMD FP multiply
def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>;
@@ -1620,38 +1620,38 @@ def : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>;
def : InstRW<[V2Wr_VFMAL, V2Rd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>;
// ASIMD FP round, D-form F32 and Q-form F64
-def : InstRW<[V2Write_3cyc_1V02],
+def : InstRW<[V2Write_3c_1V02],
(instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
"^FRINT(32|64)[XZ]v2f(32|64)$")>;
// ASIMD FP round, D-form F16 and Q-form F32
-def : InstRW<[V2Write_4cyc_2V02],
+def : InstRW<[V2Write_4c_2V02],
(instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
"^FRINT(32|64)[XZ]v4f32$")>;
// ASIMD FP round, Q-form F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
// ASIMD FP square root, D-form, F16
-def : InstRW<[V2Write_7cyc_1V02_7rc], (instrs FSQRTv4f16)>;
+def : InstRW<[V2Write_7c_1V02_7rc], (instrs FSQRTv4f16)>;
// ASIMD FP square root, D-form, F32
-def : InstRW<[V2Write_10cyc_1V02_5rc], (instrs FSQRTv2f32)>;
+def : InstRW<[V2Write_10c_1V02_5rc], (instrs FSQRTv2f32)>;
// ASIMD FP square root, Q-form, F16
-def : InstRW<[V2Write_13cyc_1V02_13rc], (instrs FSQRTv8f16)>;
+def : InstRW<[V2Write_13c_1V02_13rc], (instrs FSQRTv8f16)>;
// ASIMD FP square root, Q-form, F32
-def : InstRW<[V2Write_10cyc_1V02_9rc], (instrs FSQRTv4f32)>;
+def : InstRW<[V2Write_10c_1V02_9rc], (instrs FSQRTv4f32)>;
// ASIMD FP square root, Q-form, F64
-def : InstRW<[V2Write_16cyc_1V02_15rc], (instrs FSQRTv2f64)>;
+def : InstRW<[V2Write_16c_1V02_15rc], (instrs FSQRTv2f64)>;
// ASIMD BFloat16 (BF16) instructions
// -----------------------------------------------------------------------------
// ASIMD convert, F32 to BF16
-def : InstRW<[V2Write_4cyc_2V02], (instrs BFCVTN, BFCVTN2)>;
+def : InstRW<[V2Write_4c_2V02], (instrs BFCVTN, BFCVTN2)>;
// ASIMD dot product
def : InstRW<[V2Wr_VBFDOT, V2Rd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>;
@@ -1664,7 +1664,7 @@ def : InstRW<[V2Wr_VBFMAL, V2Rd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT,
BFMLALTIdx)>;
// Scalar convert, F32 to BF16
-def : InstRW<[V2Write_3cyc_1V02], (instrs BFCVT)>;
+def : InstRW<[V2Write_3c_1V02], (instrs BFCVT)>;
// ASIMD miscellaneous instructions
// -----------------------------------------------------------------------------
@@ -1683,317 +1683,317 @@ def : InstRW<[V2Write_3cyc_1V02], (instrs BFCVT)>;
// ASIMD transpose
// ASIMD unzip/zip
// Handled by SchedAlias<WriteV[dq], ...>
-def : InstRW<[V2Write_0or2cyc_1V], (instrs MOVID, MOVIv2d_ns)>;
+def : InstRW<[V2Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;
// ASIMD duplicate, gen reg
-def : InstRW<[V2Write_3cyc_1M0], (instregex "^DUPv.+gpr")>;
+def : InstRW<[V2Write_3c_1M0], (instregex "^DUPv.+gpr")>;
// ASIMD extract narrow, saturating
-def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
+def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
// ASIMD reciprocal and square root estimate, D-form U32
-def : InstRW<[V2Write_3cyc_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>;
+def : InstRW<[V2Write_3c_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>;
// ASIMD reciprocal and square root estimate, Q-form U32
-def : InstRW<[V2Write_4cyc_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>;
+def : InstRW<[V2Write_4c_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>;
// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms
-def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPEv1f16, FRECPEv1i32,
- FRECPEv1i64, FRECPEv2f32,
- FRSQRTEv1f16, FRSQRTEv1i32,
- FRSQRTEv1i64, FRSQRTEv2f32)>;
+def : InstRW<[V2Write_3c_1V02], (instrs FRECPEv1f16, FRECPEv1i32,
+ FRECPEv1i64, FRECPEv2f32,
+ FRSQRTEv1f16, FRSQRTEv1i32,
+ FRSQRTEv1i64, FRSQRTEv2f32)>;
// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32
-def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPEv4f16, FRECPEv4f32,
- FRSQRTEv4f16, FRSQRTEv4f32)>;
+def : InstRW<[V2Write_4c_2V02], (instrs FRECPEv4f16, FRECPEv4f32,
+ FRSQRTEv4f16, FRSQRTEv4f32)>;
// ASIMD reciprocal and square root estimate, Q-form F16
-def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
+def : InstRW<[V2Write_6c_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>;
// ASIMD reciprocal exponent
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRECPXv")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FRECPXv")>;
// ASIMD reciprocal step
-def : InstRW<[V2Write_4cyc_1V], (instregex "^FRECPS(32|64|v)",
- "^FRSQRTS(32|64|v)")>;
+def : InstRW<[V2Write_4c_1V], (instregex "^FRECPS(32|64|v)",
+ "^FRSQRTS(32|64|v)")>;
// ASIMD table lookup, 1 or 2 table regs
-def : InstRW<[V2Write_2cyc_1V01], (instrs TBLv8i8One, TBLv16i8One,
- TBLv8i8Two, TBLv16i8Two)>;
+def : InstRW<[V2Write_2c_1V01], (instrs TBLv8i8One, TBLv16i8One,
+ TBLv8i8Two, TBLv16i8Two)>;
// ASIMD table lookup, 3 table regs
-def : InstRW<[V2Write_4cyc_2V01], (instrs TBLv8i8Three, TBLv16i8Three)>;
+def : InstRW<[V2Write_4c_2V01], (instrs TBLv8i8Three, TBLv16i8Three)>;
// ASIMD table lookup, 4 table regs
-def : InstRW<[V2Write_4cyc_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>;
+def : InstRW<[V2Write_4c_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>;
// ASIMD table lookup extension, 2 table reg
-def : InstRW<[V2Write_4cyc_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;
+def : InstRW<[V2Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;
// ASIMD table lookup extension, 3 table reg
-def : InstRW<[V2Write_6cyc_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;
+def : InstRW<[V2Write_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;
// ASIMD table lookup extension, 4 table reg
-def : InstRW<[V2Write_6cyc_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;
+def : InstRW<[V2Write_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;
// ASIMD transfer, element to gen reg
-def : InstRW<[V2Write_2cyc_2V01], (instregex "^[SU]MOVv")>;
+def : InstRW<[V2Write_2c_2V01], (instregex "^[SU]MOVv")>;
// ASIMD transfer, gen reg to element
-def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
+def : InstRW<[V2Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
// ASIMD load instructions
// -----------------------------------------------------------------------------
// ASIMD load, 1 element, multiple, 1 reg, D-form
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_1L],
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_1L],
(instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 1 reg, Q-form
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_1L],
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_1L],
(instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 2 reg, D-form
-def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_2L],
+def : InstRW<[V2Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_2L],
(instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 2 reg, Q-form
-def : InstRW<[V2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_2L],
+def : InstRW<[V2Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_2L],
(instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 3 reg, D-form
-def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_3L],
+def : InstRW<[V2Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_3L],
(instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 3 reg, Q-form
-def : InstRW<[V2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_3L],
+def : InstRW<[V2Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_3L],
(instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, multiple, 4 reg, D-form
-def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_7cyc_4L],
+def : InstRW<[V2Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_7c_4L],
(instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, multiple, 4 reg, Q-form
-def : InstRW<[V2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_7cyc_4L],
+def : InstRW<[V2Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_7c_4L],
(instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 1 element, one lane, B/H/S
// ASIMD load, 1 element, one lane, D
-def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
// ASIMD load, 1 element, all lanes, D-form, B/H/S
// ASIMD load, 1 element, all lanes, D-form, D
-def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 1 element, all lanes, Q-form
-def : InstRW<[V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 2 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
// ASIMD load, 2 element, multiple, Q-form, B/H/S
// ASIMD load, 2 element, multiple, Q-form, D
-def : InstRW<[V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 2 element, one lane, B/H
// ASIMD load, 2 element, one lane, S
// ASIMD load, 2 element, one lane, D
-def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
// ASIMD load, 2 element, all lanes, D-form, B/H/S
// ASIMD load, 2 element, all lanes, D-form, D
-def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 2 element, all lanes, Q-form
-def : InstRW<[V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 3 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
// ASIMD load, 3 element, multiple, Q-form, B/H/S
// ASIMD load, 3 element, multiple, Q-form, D
-def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 3 element, one lane, B/H
// ASIMD load, 3 element, one lane, S
// ASIMD load, 3 element, one lane, D
-def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
// ASIMD load, 3 element, all lanes, D-form, B/H/S
// ASIMD load, 3 element, all lanes, D-form, D
-def : InstRW<[V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 3 element, all lanes, Q-form, B/H/S
// ASIMD load, 3 element, all lanes, Q-form, D
-def : InstRW<[V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 4 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
// ASIMD load, 4 element, multiple, Q-form, B/H/S
// ASIMD load, 4 element, multiple, Q-form, D
-def : InstRW<[V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_9cyc_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD load, 4 element, one lane, B/H
// ASIMD load, 4 element, one lane, S
// ASIMD load, 4 element, one lane, D
-def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
// ASIMD load, 4 element, all lanes, D-form, B/H/S
// ASIMD load, 4 element, all lanes, D-form, D
-def : InstRW<[V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
// ASIMD load, 4 element, all lanes, Q-form, B/H/S
// ASIMD load, 4 element, all lanes, Q-form, D
-def : InstRW<[V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
// ASIMD store instructions
// -----------------------------------------------------------------------------
// ASIMD store, 1 element, multiple, 1 reg, D-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 1 reg, Q-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 2 reg, D-form
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 2 reg, Q-form
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 3 reg, D-form
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 3 reg, Q-form
-def : InstRW<[V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_2c_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, multiple, 4 reg, D-form
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
// ASIMD store, 1 element, multiple, 4 reg, Q-form
-def : InstRW<[V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_2cyc_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_2c_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_2c_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 1 element, one lane, B/H/S
// ASIMD store, 1 element, one lane, D
-def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST1i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST1i(8|16|32|64)_POST$")>;
// ASIMD store, 2 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
// ASIMD store, 2 element, multiple, Q-form, B/H/S
// ASIMD store, 2 element, multiple, Q-form, D
-def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_4c_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_4c_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 2 element, one lane, B/H/S
// ASIMD store, 2 element, one lane, D
-def : InstRW<[V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_4cyc_1L01_2V01], (instregex "ST2i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST2i(8|16|32|64)_POST$")>;
// ASIMD store, 3 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_5c_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_5c_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
// ASIMD store, 3 element, multiple, Q-form, B/H/S
// ASIMD store, 3 element, multiple, Q-form, D
-def : InstRW<[V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
+def : InstRW<[V2Write_6c_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
// ASIMD store, 3 element, one lane, B/H
// ASIMD store, 3 element, one lane, S
// ASIMD store, 3 element, one lane, D
-def : InstRW<[V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>;
-def : InstRW<[WriteAdr, V2Write_5cyc_2L01_4V01], (instregex "ST3i(8|16|32|64)_POST$")>;
+def : InstRW<[V2Write_5c_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>;
+def : InstRW<[WriteAdr, V2Write_5c_2L01_4V01], (instregex "ST3i(8|16|32|64)_POST$")>;
// ASIMD store, 4 element, multiple, D-form, B/H/S
-def : InstRW<[V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
+def : InstRW<[V2Write_6c_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
// ASIMD store, 4 element, multiple, Q-form, B/H/S
-def : InstRW<[V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>;
-def : InstRW<[WriteAdr, V2Write_7cyc_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
+def : InstRW<[V2Write_7c_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>;
+def : InstRW<[WriteAdr, V2Write_7c_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
// ASIMD store, 4 element, multiple, Q-form, D
-def : InstRW<[V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)$")>;
-def : InstRW<[WriteAdr, V2Write_5cyc_4L01_8V01], (instregex "ST4Fourv(2d)_POST$")>;
+def : InstRW<[V2Write_5c_4L01_8V01], (instregex "ST4Fourv(2d)$")>;
+def : InstRW<[WriteAdr, V2Write_5c_4L01_8V01], (instregex "ST4Fourv(2d)_POST$")>;
// ASIMD store, 4 element, one lane, B/H/S
-def : InstRW<[V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)$")>;
-def : InstRW<[WriteAdr, V2Write_6cyc_1L01_3V01], (instregex "ST4i(8|16|32)_POST$")>;
+def : InstRW<[V2Write_6c_1L01_3V01], (instregex "ST4i(8|16|32)$")>;
+def : InstRW<[WriteAdr, V2Write_6c_1L01_3V01], (instregex "ST4i(8|16|32)_POST$")>;
// ASIMD store, 4 element, one lane, D
-def : InstRW<[V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)$")>;
-def : InstRW<[WriteAdr, V2Write_4cyc_2L01_4V01], (instregex "ST4i(64)_POST$")>;
+def : InstRW<[V2Write_4c_2L01_4V01], (instregex "ST4i(64)$")>;
+def : InstRW<[WriteAdr, V2Write_4c_2L01_4V01], (instregex "ST4i(64)_POST$")>;
// Cryptography extensions
// -----------------------------------------------------------------------------
// Crypto AES ops
-def : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
// Crypto polynomial (64x64) multiply long
-def : InstRW<[V2Write_2cyc_1V], (instrs PMULLv1i64, PMULLv2i64)>;
+def : InstRW<[V2Write_2c_1V], (instrs PMULLv1i64, PMULLv2i64)>;
// Crypto SHA1 hash acceleration op
// Crypto SHA1 schedule acceleration ops
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA1(H|SU0|SU1)")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;
// Crypto SHA1 hash acceleration ops
// Crypto SHA256 hash acceleration ops
-def : InstRW<[V2Write_4cyc_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;
+def : InstRW<[V2Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;
// Crypto SHA256 schedule acceleration ops
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA256SU[01]")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^SHA256SU[01]")>;
// Crypto SHA512 hash acceleration ops
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;
// Crypto SHA3 ops
-def : InstRW<[V2Write_2cyc_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;
+def : InstRW<[V2Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;
// Crypto SM3 ops
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",
- "^SM3TT[12][AB]$")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",
+ "^SM3TT[12][AB]$")>;
// Crypto SM4 ops
-def : InstRW<[V2Write_4cyc_1V0], (instrs SM4E, SM4ENCKEY)>;
+def : InstRW<[V2Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;
// CRC
// -----------------------------------------------------------------------------
@@ -2004,31 +2004,31 @@ def : InstRW<[V2Wr_CRC, V2Rd_CRC], (instregex "^CRC32")>;
// -----------------------------------------------------------------------------
// Loop control, based on predicate
-def : InstRW<[V2Write_2or3cyc_1M], (instrs BRKA_PPmP, BRKA_PPzP,
- BRKB_PPmP, BRKB_PPzP)>;
+def : InstRW<[V2Write_2or3c_1M], (instrs BRKA_PPmP, BRKA_PPzP,
+ BRKB_PPmP, BRKB_PPzP)>;
// Loop control, based on predicate and flag setting
-def : InstRW<[V2Write_3or4cyc_2M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;
+def : InstRW<[V2Write_3or4c_2M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;
// Loop control, propagating
-def : InstRW<[V2Write_2or3cyc_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP,
- BRKPB_PPzPP)>;
+def : InstRW<[V2Write_2or3c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP,
+ BRKPB_PPzPP)>;
// Loop control, propagating and flag setting
-def : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,
- BRKPBS_PPzPP)>;
+def : InstRW<[V2Write_3or4c_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,
+ BRKPBS_PPzPP)>;
// Loop control, based on GPR
-def : InstRW<[V2Write_3cyc_2M],
+def : InstRW<[V2Write_3c_2M],
(instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;
-def : InstRW<[V2Write_3cyc_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;
+def : InstRW<[V2Write_3c_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;
// Loop terminate
-def : InstRW<[V2Write_1cyc_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;
+def : InstRW<[V2Write_1c_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;
// Predicate counting scalar
-def : InstRW<[V2Write_2cyc_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;
-def : InstRW<[V2Write_2cyc_1M],
+def : InstRW<[V2Write_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;
+def : InstRW<[V2Write_2c_1M],
(instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",
"^SQ(DEC|INC)[BHWD]_XPiWdI",
"^UQ(DEC|INC)[BHWD]_WPiI")>;
@@ -2037,57 +2037,57 @@ def : InstRW<[V2Write_2cyc_1M],
def : InstRW<[V2Write_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI")>;
// Predicate counting scalar, active predicate
-def : InstRW<[V2Write_2cyc_1M],
+def : InstRW<[V2Write_2c_1M],
(instregex "^CNTP_XPP_[BHSD]",
"^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",
"^(UQDEC|UQINC)P_WP_[BHSD]",
"^(SQDEC|SQINC)P_XPWd_[BHSD]")>;
// Predicate counting vector, active predicate
-def : InstRW<[V2Write_7cyc_1M_1M0_1V],
+def : InstRW<[V2Write_7c_1M_1M0_1V],
(instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;
// Predicate logical
-def : InstRW<[V2Write_1or2cyc_1M0],
+def : InstRW<[V2Write_1or2c_1M0],
(instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;
// Predicate logical, flag setting
-def : InstRW<[V2Write_1or2cyc_1M0_1M],
+def : InstRW<[V2Write_1or2c_1M0_1M],
(instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
// Predicate reverse
-def : InstRW<[V2Write_2cyc_1M], (instregex "^REV_PP_[BHSD]")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^REV_PP_[BHSD]")>;
// Predicate select
-def : InstRW<[V2Write_1cyc_1M0], (instrs SEL_PPPP)>;
+def : InstRW<[V2Write_1c_1M0], (instrs SEL_PPPP)>;
// Predicate set
-def : InstRW<[V2Write_2cyc_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
// Predicate set/initialize, set flags
-def : InstRW<[V2Write_3cyc_2M], (instregex "^PTRUES_[BHSD]")>;
+def : InstRW<[V2Write_3c_2M], (instregex "^PTRUES_[BHSD]")>;
// Predicate find first/next
-def : InstRW<[V2Write_2cyc_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[V2Write_1cyc_1M], (instrs PTEST_PP)>;
+def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP)>;
// Predicate transpose
-def : InstRW<[V2Write_2cyc_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
// Predicate unpack and widen
-def : InstRW<[V2Write_2cyc_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;
+def : InstRW<[V2Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;
// Predicate zip/unzip
-def : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;
+def : InstRW<[V2Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;
// SVE integer instructions
// -----------------------------------------------------------------------------
// Arithmetic, absolute
diff
-def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
- "^[SU]ABD_ZPZZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",
+ "^[SU]ABD_ZPZZ_[BHSD]")>;
// Arithmetic, absolute
diff accum
def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;
@@ -2096,10 +2096,10 @@ def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;
def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;
// Arithmetic, absolute
diff long
-def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;
// Arithmetic, basic
-def : InstRW<[V2Write_2cyc_1V],
+def : InstRW<[V2Write_2c_1V],
(instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
"^(ADD|SUB)_ZZZ_[BHSD]",
"^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",
@@ -2112,7 +2112,7 @@ def : InstRW<[V2Write_2cyc_1V],
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;
// Arithmetic, complex
-def : InstRW<[V2Write_2cyc_1V],
+def : InstRW<[V2Write_2c_1V],
(instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",
"^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",
"^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",
@@ -2121,17 +2121,17 @@ def : InstRW<[V2Write_2cyc_1V],
"^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;
// Arithmetic, large integer
-def : InstRW<[V2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;
// Arithmetic, pairwise add
-def : InstRW<[V2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;
// Arithmetic, pairwise add and accum long
def : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA],
(instregex "^[SU]ADALP_ZPmZ_[HSD]")>;
// Arithmetic, shift
-def : InstRW<[V2Write_2cyc_1V13],
+def : InstRW<[V2Write_2c_1V13],
(instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
"^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
"^(ASR|LSL|LSR)_ZPmI_[BHSD]",
@@ -2144,14 +2144,14 @@ def : InstRW<[V2Write_2cyc_1V13],
def : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>;
// Arithmetic, shift by immediate
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]",
- "^[SU]SHLL[BT]_ZZI_[HSD]")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]",
+ "^[SU]SHLL[BT]_ZZI_[HSD]")>;
// Arithmetic, shift by immediate and insert
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;
// Arithmetic, shift complex
-def : InstRW<[V2Write_4cyc_1V13],
+def : InstRW<[V2Write_4c_1V13],
(instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",
"^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",
"^[SU]QR?SHL_ZPZZ_[BHSD]",
@@ -2160,32 +2160,32 @@ def : InstRW<[V2Write_4cyc_1V13],
"^UQR?SHRN[BT]_ZZI_[BHS]")>;
// Arithmetic, shift right for divide
-def : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;
+def : InstRW<[V2Write_4c_1V13], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;
// Arithmetic, shift rounding
-def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",
- "^[SU]RSHL_ZPZZ_[BHSD]",
- "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;
+def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",
+ "^[SU]RSHL_ZPZZ_[BHSD]",
+ "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;
// Bit manipulation
-def : InstRW<[V2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;
+def : InstRW<[V2Write_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;
// Bitwise select
-def : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;
// Count/reverse bits
-def : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;
// Broadcast logical bitmask immediate to vector
-def : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>;
+def : InstRW<[V2Write_2c_1V], (instrs DUPM_ZI)>;
// Compare and set flags
-def : InstRW<[V2Write_4or5cyc_1V0_1M0],
+def : InstRW<[V2Write_4or5c_1V0_1M0],
(instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",
"^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;
// Complex add
-def : InstRW<[V2Write_2cyc_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;
// Complex dot product 8-bit element
def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
@@ -2201,37 +2201,37 @@ def : InstRW<[V2Wr_ZCMABHS, V2Rd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]",
def : InstRW<[V2Wr_ZCMAD, V2Rd_ZCMAD], (instrs CMLA_ZZZ_D)>;
// Conditional extract operations, scalar form
-def : InstRW<[V2Write_8cyc_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;
+def : InstRW<[V2Write_8c_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;
// Conditional extract operations, SIMD&FP scalar and vector forms
-def : InstRW<[V2Write_3cyc_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",
- "^COMPACT_ZPZ_[SD]",
- "^SPLICE_ZPZZ?_[BHSD]")>;
+def : InstRW<[V2Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",
+ "^COMPACT_ZPZ_[SD]",
+ "^SPLICE_ZPZZ?_[BHSD]")>;
// Convert to floating point, 64b to float or convert to double
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",
+def : InstRW<[V2Write_3c_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",
"^[SU]CVTF_ZPmZ_StoD")>;
// Convert to floating point, 32b to single or half
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
// Convert to floating point, 16b to half
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;
// Copy, scalar
-def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;
+def : InstRW<[V2Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;
// Copy, scalar SIMD&FP or imm
-def : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",
- "^CPY_ZPzI_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",
+ "^CPY_ZPzI_[BHSD]")>;
// Divides, 32 bit
-def : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",
- "^[SU]DIV_ZPZZ_S")>;
+def : InstRW<[V2Write_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",
+ "^[SU]DIV_ZPZZ_S")>;
// Divides, 64 bit
-def : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",
- "^[SU]DIV_ZPZZ_D")>;
+def : InstRW<[V2Write_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",
+ "^[SU]DIV_ZPZZ_D")>;
// Dot product, 8 bit
def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S")>;
@@ -2243,52 +2243,52 @@ def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ
def : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_D")>;
// Duplicate, immediate and indexed form
-def : InstRW<[V2Write_2cyc_1V], (instregex "^DUP_ZI_[BHSD]",
- "^DUP_ZZI_[BHSDQ]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^DUP_ZI_[BHSD]",
+ "^DUP_ZZI_[BHSDQ]")>;
// Duplicate, scalar form
-def : InstRW<[V2Write_3cyc_1M0], (instregex "^DUP_ZR_[BHSD]")>;
+def : InstRW<[V2Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]")>;
// Extend, sign or zero
-def : InstRW<[V2Write_2cyc_1V13], (instregex "^[SU]XTB_ZPmZ_[HSD]",
- "^[SU]XTH_ZPmZ_[SD]",
- "^[SU]XTW_ZPmZ_[D]")>;
+def : InstRW<[V2Write_2c_1V13], (instregex "^[SU]XTB_ZPmZ_[HSD]",
+ "^[SU]XTH_ZPmZ_[SD]",
+ "^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[V2Write_2cyc_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[V2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
// Extract narrow saturating
-def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
- "^SQXTUN[BT]_ZZ_[BHS]")>;
+def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
+ "^SQXTUN[BT]_ZZ_[BHS]")>;
// Extract/insert operation, SIMD and FP scalar form
-def : InstRW<[V2Write_3cyc_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]",
- "^INSR_ZV_[BHSD]")>;
+def : InstRW<[V2Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]",
+ "^INSR_ZV_[BHSD]")>;
// Extract/insert operation, scalar
-def : InstRW<[V2Write_6cyc_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]",
- "^INSR_ZR_[BHSD]")>;
+def : InstRW<[V2Write_6c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]",
+ "^INSR_ZR_[BHSD]")>;
// Histogram operations
-def : InstRW<[V2Write_2cyc_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",
- "^HISTSEG_ZZZ")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",
+ "^HISTSEG_ZZZ")>;
// Horizontal operations, B, H, S form, immediate operands only
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^INDEX_II_[BHS]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^INDEX_II_[BHS]")>;
// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar
// operands only / immediate, scalar operands
-def : InstRW<[V2Write_7cyc_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;
+def : InstRW<[V2Write_7c_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;
// Horizontal operations, D form, immediate operands only
-def : InstRW<[V2Write_5cyc_2V02], (instrs INDEX_II_D)>;
+def : InstRW<[V2Write_5c_2V02], (instrs INDEX_II_D)>;
// Horizontal operations, D form, scalar, immediate operands)/ scalar operands
// only / immediate, scalar operands
-def : InstRW<[V2Write_8cyc_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D")>;
+def : InstRW<[V2Write_8c_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D")>;
// Logical
-def : InstRW<[V2Write_2cyc_1V],
+def : InstRW<[V2Write_2c_1V],
(instregex "^(AND|EOR|ORR)_ZI",
"^(AND|BIC|EOR|ORR)_ZZZ",
"^EOR(BT|TB)_ZZZ_[BHSD]",
@@ -2296,37 +2296,37 @@ def : InstRW<[V2Write_2cyc_1V],
"^NOT_ZPmZ_[BHSD]")>;
// Max/min, basic and pairwise
-def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
- "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",
- "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",
+ "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",
+ "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;
// Matching operations
// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the
// latency for this instruction is 4 cycles.
-def : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;
+def : InstRW<[V2Write_2or3c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;
// Matrix multiply-accumulate
def : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
// Move prefix
-def : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",
- "^MOVPRFX_ZZ")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",
+ "^MOVPRFX_ZZ")>;
// Multiply, B, H, S element size
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",
- "^MUL_ZPZZ_[BHS]",
- "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",
- "^[SU]MULH_ZPZZ_[BHS]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",
+ "^MUL_ZPZZ_[BHS]",
+ "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",
+ "^[SU]MULH_ZPZZ_[BHS]")>;
// Multiply, D element size
-def : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",
- "^MUL_ZPZZ_D",
- "^[SU]MULH_(ZPmZ|ZZZ)_D",
- "^[SU]MULH_ZPZZ_D")>;
+def : InstRW<[V2Write_5c_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",
+ "^MUL_ZPZZ_D",
+ "^[SU]MULH_(ZPmZ|ZZZ)_D",
+ "^[SU]MULH_ZPZZ_D")>;
// Multiply long
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",
- "^[SU]MULL[BT]_ZZZ_[HSD]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",
+ "^[SU]MULL[BT]_ZZZ_[HSD]")>;
// Multiply accumulate, B, H, S element size
def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS],
@@ -2350,15 +2350,15 @@ def : InstRW<[V2Wr_ZMASQL, V2Rd_ZMASQ],
"^SQDML[AS]L[BT]_ZZZI_[SD]")>;
// Multiply saturating doubling high, B, H, S element size
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULH_ZZZ_[BHS]",
- "^SQDMULH_ZZZI_[HS]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^SQDMULH_ZZZ_[BHS]",
+ "^SQDMULH_ZZZI_[HS]")>;
// Multiply saturating doubling high, D element size
-def : InstRW<[V2Write_5cyc_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;
+def : InstRW<[V2Write_5c_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;
// Multiply saturating doubling long
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",
- "^SQDMULL[BT]_ZZZI_[SD]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",
+ "^SQDMULL[BT]_ZZZI_[SD]")>;
// Multiply saturating rounding doubling regular/complex accumulate, B, H, S
// element size
@@ -2373,157 +2373,157 @@ def : InstRW<[V2Wr_ZMASQD, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D",
"^SQRDCMLAH_ZZZ_D")>;
// Multiply saturating rounding doubling regular/complex, B, H, S element size
-def : InstRW<[V2Write_4cyc_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]",
- "^SQRDMULH_ZZZI_[HS]")>;
+def : InstRW<[V2Write_4c_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]",
+ "^SQRDMULH_ZZZI_[HS]")>;
// Multiply saturating rounding doubling regular/complex, D element size
-def : InstRW<[V2Write_5cyc_2V02], (instregex "^SQRDMULH_ZZZI?_D")>;
+def : InstRW<[V2Write_5c_2V02], (instregex "^SQRDMULH_ZZZI?_D")>;
// Multiply/multiply long, (8x8) polynomial
-def : InstRW<[V2Write_2cyc_1V23], (instregex "^PMUL_ZZZ_B",
- "^PMULL[BT]_ZZZ_[HDQ]")>;
+def : InstRW<[V2Write_2c_1V23], (instregex "^PMUL_ZZZ_B",
+ "^PMULL[BT]_ZZZ_[HDQ]")>;
// Predicate counting vector
-def : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;
// Reciprocal estimate
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;
// Reduction, arithmetic, B form
-def : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
+def : InstRW<[V2Write_9c_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
// Reduction, arithmetic, H form
-def : InstRW<[V2Write_8cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;
+def : InstRW<[V2Write_8c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;
// Reduction, arithmetic, S form
-def : InstRW<[V2Write_6cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;
+def : InstRW<[V2Write_6c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;
// Reduction, arithmetic, D form
-def : InstRW<[V2Write_4cyc_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
+def : InstRW<[V2Write_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;
// Reduction, logical
-def : InstRW<[V2Write_6cyc_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;
+def : InstRW<[V2Write_6c_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;
// Reverse, vector
-def : InstRW<[V2Write_2cyc_1V], (instregex "^REV_ZZ_[BHSD]",
- "^REVB_ZPmZ_[HSD]",
- "^REVH_ZPmZ_[SD]",
- "^REVW_ZPmZ_D")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^REV_ZZ_[BHSD]",
+ "^REVB_ZPmZ_[HSD]",
+ "^REVH_ZPmZ_[SD]",
+ "^REVW_ZPmZ_D")>;
// Select, vector form
-def : InstRW<[V2Write_2cyc_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;
// Table lookup
-def : InstRW<[V2Write_2cyc_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;
// Table lookup extension
-def : InstRW<[V2Write_2cyc_1V], (instregex "^TBX_ZZZ_[BHSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^TBX_ZZZ_[BHSD]")>;
// Transpose, vector form
-def : InstRW<[V2Write_2cyc_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;
// Unpack and extend
-def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;
// Zip/unzip
-def : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;
// SVE floating-point instructions
// -----------------------------------------------------------------------------
// Floating point absolute value/
diff erence
-def : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",
- "^FABD_ZPZZ_[HSD]",
- "^FABS_ZPmZ_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",
+ "^FABD_ZPZZ_[HSD]",
+ "^FABS_ZPmZ_[HSD]")>;
// Floating point arithmetic
-def : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",
- "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",
- "^FADDP_ZPmZZ_[HSD]",
- "^FNEG_ZPmZ_[HSD]",
- "^FSUBR_ZPm[IZ]_[HSD]",
- "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",
+ "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",
+ "^FADDP_ZPmZZ_[HSD]",
+ "^FNEG_ZPmZ_[HSD]",
+ "^FSUBR_ZPm[IZ]_[HSD]",
+ "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;
// Floating point associative add, F16
-def : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>;
+def : InstRW<[V2Write_10c_1V1_9rc], (instrs FADDA_VPZ_H)>;
// Floating point associative add, F32
-def : InstRW<[V2Write_6cyc_1V1_5rc], (instrs FADDA_VPZ_S)>;
+def : InstRW<[V2Write_6c_1V1_5rc], (instrs FADDA_VPZ_S)>;
// Floating point associative add, F64
-def : InstRW<[V2Write_4cyc_1V], (instrs FADDA_VPZ_D)>;
+def : InstRW<[V2Write_4c_1V], (instrs FADDA_VPZ_D)>;
// Floating point compare
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",
- "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",
- "^FCM(LE|LT)_PPzZ0_[HSD]",
- "^FCMUO_PPzZZ_[HSD]")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",
+ "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",
+ "^FCM(LE|LT)_PPzZ0_[HSD]",
+ "^FCMUO_PPzZZ_[HSD]")>;
// Floating point complex add
-def : InstRW<[V2Write_3cyc_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;
+def : InstRW<[V2Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;
// Floating point complex multiply add
def : InstRW<[V2Wr_ZFCMA, ReadDefault, V2Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;
def : InstRW<[V2Wr_ZFCMA, V2Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;
// Floating point convert, long or narrow (F16 to F32 or F32 to F16)
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
- "^FCVTLT_ZPmZ_HtoS",
- "^FCVTNT_ZPmZ_StoH")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",
+ "^FCVTLT_ZPmZ_HtoS",
+ "^FCVTNT_ZPmZ_StoH")>;
// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32
// or F64 to F16)
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",
- "^FCVTLT_ZPmZ_StoD",
- "^FCVTNT_ZPmZ_DtoS")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",
+ "^FCVTLT_ZPmZ_StoD",
+ "^FCVTNT_ZPmZ_DtoS")>;
// Floating point convert, round to odd
-def : InstRW<[V2Write_3cyc_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;
+def : InstRW<[V2Write_3c_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;
// Floating point base2 log, F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;
// Floating point base2 log, F32
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;
// Floating point base2 log, F64
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;
// Floating point convert to integer, F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;
// Floating point convert to integer, F32
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;
// Floating point convert to integer, F64
-def : InstRW<[V2Write_3cyc_1V02],
+def : InstRW<[V2Write_3c_1V02],
(instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;
// Floating point copy
-def : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]",
- "^FDUP_ZI_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]",
+ "^FDUP_ZI_[HSD]")>;
// Floating point divide, F16
-def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;
+def : InstRW<[V2Write_13c_1V02_12rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;
// Floating point divide, F32
-def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;
+def : InstRW<[V2Write_10c_1V02_9rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;
// Floating point divide, F64
-def : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;
+def : InstRW<[V2Write_15c_1V02_14rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;
// Floating point min/max pairwise
-def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;
// Floating point min/max
-def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",
- "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",
+ "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;
// Floating point multiply
-def : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
- "^FMULX_ZPZZ_[HSD]",
- "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",
- "^FMUL_ZPZ[IZ]_[HSD]")>;
+def : InstRW<[V2Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",
+ "^FMULX_ZPZZ_[HSD]",
+ "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",
+ "^FMUL_ZPZ[IZ]_[HSD]")>;
// Floating point multiply accumulate
def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA],
@@ -2537,61 +2537,61 @@ def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA],
def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;
// Floating point reciprocal estimate, F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;
// Floating point reciprocal estimate, F32
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;
// Floating point reciprocal estimate, F64
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;
// Floating point reciprocal step
-def : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;
+def : InstRW<[V2Write_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;
// Floating point reduction, F16
-def : InstRW<[V2Write_8cyc_4V],
+def : InstRW<[V2Write_8c_4V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>;
// Floating point reduction, F32
-def : InstRW<[V2Write_6cyc_3V],
+def : InstRW<[V2Write_6c_3V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>;
// Floating point reduction, F64
-def : InstRW<[V2Write_4cyc_2V],
+def : InstRW<[V2Write_4c_2V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>;
// Floating point round to integral, F16
-def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
+def : InstRW<[V2Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
// Floating point round to integral, F32
-def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
+def : InstRW<[V2Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
// Floating point round to integral, F64
-def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
+def : InstRW<[V2Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
// Floating point square root, F16
-def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FSQRT_ZPmZ_H")>;
+def : InstRW<[V2Write_13c_1V02_12rc], (instregex "^FSQRT_ZPmZ_H")>;
// Floating point square root, F32
-def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FSQRT_ZPmZ_S")>;
+def : InstRW<[V2Write_10c_1V02_9rc], (instregex "^FSQRT_ZPmZ_S")>;
// Floating point square root, F64
-def : InstRW<[V2Write_16cyc_1V02_14rc], (instregex "^FSQRT_ZPmZ_D")>;
+def : InstRW<[V2Write_16c_1V02_14rc], (instregex "^FSQRT_ZPmZ_D")>;
// Floating point trigonometric exponentiation
-def : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;
+def : InstRW<[V2Write_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;
// Floating point trigonometric multiply add
-def : InstRW<[V2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]")>;
+def : InstRW<[V2Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]")>;
// Floating point trigonometric, miscellaneous
-def : InstRW<[V2Write_3cyc_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;
+def : InstRW<[V2Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;
// SVE BFloat16 (BF16) instructions
// -----------------------------------------------------------------------------
// Convert, F32 to BF16
-def : InstRW<[V2Write_4cyc_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
+def : InstRW<[V2Write_4c_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;
// Dot product
def : InstRW<[V2Wr_ZBFDOT, V2Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
@@ -2606,101 +2606,101 @@ def : InstRW<[V2Wr_ZBFMAL, V2Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>;
// -----------------------------------------------------------------------------
// Load vector
-def : InstRW<[V2Write_6cyc_1L], (instrs LDR_ZXI)>;
+def : InstRW<[V2Write_6c_1L], (instrs LDR_ZXI)>;
// Load predicate
-def : InstRW<[V2Write_6cyc_1L_1M], (instrs LDR_PXI)>;
+def : InstRW<[V2Write_6c_1L_1M], (instrs LDR_PXI)>;
// Contiguous load, scalar + imm
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
- "^LD1S?B_[HSD]_IMM$",
- "^LD1S?H_[SD]_IMM$",
- "^LD1S?W_D_IMM$" )>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",
+ "^LD1S?B_[HSD]_IMM$",
+ "^LD1S?H_[SD]_IMM$",
+ "^LD1S?W_D_IMM$" )>;
// Contiguous load, scalar + scalar
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]$",
- "^LD1S?B_[HSD]$",
- "^LD1S?H_[SD]$",
- "^LD1S?W_D$" )>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]$",
+ "^LD1S?B_[HSD]$",
+ "^LD1S?H_[SD]$",
+ "^LD1S?W_D$" )>;
// Contiguous load broadcast, scalar + imm
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1R[BHWD]_IMM$",
- "^LD1RS?B_[HSD]_IMM$",
- "^LD1RS?H_[SD]_IMM$",
- "^LD1RW_D_IMM$",
- "^LD1RSW_IMM$",
- "^LD1RQ_[BHWD]_IMM$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",
+ "^LD1RS?B_[HSD]_IMM$",
+ "^LD1RS?H_[SD]_IMM$",
+ "^LD1RW_D_IMM$",
+ "^LD1RSW_IMM$",
+ "^LD1RQ_[BHWD]_IMM$")>;
// Contiguous load broadcast, scalar + scalar
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1RQ_[BHWD]$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;
// Non temporal load, scalar + imm
// Non temporal load, scalar + scalar
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;
// Non temporal gather load, vector + scalar 32-bit element size
-def : InstRW<[V2Write_9cyc_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S$",
- "^LDNT1S[BH]_ZZR_S$")>;
+def : InstRW<[V2Write_9c_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S$",
+ "^LDNT1S[BH]_ZZR_S$")>;
// Non temporal gather load, vector + scalar 64-bit element size
-def : InstRW<[V2Write_9cyc_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;
-def : InstRW<[V2Write_9cyc_2L_2V1], (instrs LDNT1D_ZZR_D)>;
+def : InstRW<[V2Write_9c_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;
+def : InstRW<[V2Write_9c_2L_2V1], (instrs LDNT1D_ZZR_D)>;
// Contiguous first faulting load, scalar + scalar
-def : InstRW<[V2Write_6cyc_1L_1S], (instregex "^LDFF1[BHWD]$",
- "^LDFF1S?B_[HSD]$",
- "^LDFF1S?H_[SD]$",
- "^LDFF1S?W_D$")>;
+def : InstRW<[V2Write_6c_1L_1S], (instregex "^LDFF1[BHWD]$",
+ "^LDFF1S?B_[HSD]$",
+ "^LDFF1S?H_[SD]$",
+ "^LDFF1S?W_D$")>;
// Contiguous non faulting load, scalar + imm
-def : InstRW<[V2Write_6cyc_1L], (instregex "^LDNF1[BHWD]_IMM$",
- "^LDNF1S?B_[HSD]_IMM$",
- "^LDNF1S?H_[SD]_IMM$",
- "^LDNF1S?W_D_IMM$")>;
+def : InstRW<[V2Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",
+ "^LDNF1S?B_[HSD]_IMM$",
+ "^LDNF1S?H_[SD]_IMM$",
+ "^LDNF1S?W_D_IMM$")>;
// Contiguous Load two structures to two vectors, scalar + imm
-def : InstRW<[V2Write_8cyc_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;
+def : InstRW<[V2Write_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;
// Contiguous Load two structures to two vectors, scalar + scalar
-def : InstRW<[V2Write_9cyc_2L_2V_2S], (instregex "^LD2[BHWD]$")>;
+def : InstRW<[V2Write_9c_2L_2V_2S], (instregex "^LD2[BHWD]$")>;
// Contiguous Load three structures to three vectors, scalar + imm
-def : InstRW<[V2Write_9cyc_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;
+def : InstRW<[V2Write_9c_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;
// Contiguous Load three structures to three vectors, scalar + scalar
-def : InstRW<[V2Write_10cyc_3V_3L_3S], (instregex "^LD3[BHWD]$")>;
+def : InstRW<[V2Write_10c_3V_3L_3S], (instregex "^LD3[BHWD]$")>;
// Contiguous Load four structures to four vectors, scalar + imm
-def : InstRW<[V2Write_9cyc_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;
+def : InstRW<[V2Write_9c_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;
// Contiguous Load four structures to four vectors, scalar + scalar
-def : InstRW<[V2Write_10cyc_4L_8V_4S], (instregex "^LD4[BHWD]$")>;
+def : InstRW<[V2Write_10c_4L_8V_4S], (instregex "^LD4[BHWD]$")>;
// Gather load, vector + imm, 32-bit element size
-def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
- "^GLD(FF)?1W_IMM$")>;
+def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
+ "^GLD(FF)?1W_IMM$")>;
// Gather load, vector + imm, 64-bit element size
-def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",
- "^GLD(FF)?1D_IMM$")>;
+def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",
+ "^GLD(FF)?1D_IMM$")>;
// Gather load, 32-bit scaled offset
-def : InstRW<[V2Write_10cyc_1L_8V],
+def : InstRW<[V2Write_10c_1L_8V],
(instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED$",
"^GLD(FF)?1W_[SU]XTW_SCALED")>;
// Gather load, 64-bit scaled offset
// NOTE: These instructions are not specified in the SOG.
-def : InstRW<[V2Write_10cyc_1L_4V],
+def : InstRW<[V2Write_10c_1L_4V],
(instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED$",
"^GLD(FF)?1D_([SU]XTW_)?SCALED$")>;
// Gather load, 32-bit unpacked unscaled offset
-def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
- "^GLD(FF)?1W_[SU]XTW$")>;
+def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
+ "^GLD(FF)?1W_[SU]XTW$")>;
// Gather load, 64-bit unpacked unscaled offset
// NOTE: These instructions are not specified in the SOG.
-def : InstRW<[V2Write_9cyc_1L_2V],
+def : InstRW<[V2Write_9c_1L_2V],
(instregex "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?$",
"^GLD(FF)?1D(_[SU]XTW)?$")>;
@@ -2708,120 +2708,120 @@ def : InstRW<[V2Write_9cyc_1L_2V],
// -----------------------------------------------------------------------------
// Store from predicate reg
-def : InstRW<[V2Write_1cyc_1L01], (instrs STR_PXI)>;
+def : InstRW<[V2Write_1c_1L01], (instrs STR_PXI)>;
// Store from vector reg
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instrs STR_ZXI)>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instrs STR_ZXI)>;
// Contiguous store, scalar + imm
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",
- "^ST1B_[HSD]_IMM$",
- "^ST1H_[SD]_IMM$",
- "^ST1W_D_IMM$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",
+ "^ST1B_[HSD]_IMM$",
+ "^ST1H_[SD]_IMM$",
+ "^ST1W_D_IMM$")>;
// Contiguous store, scalar + scalar
-def : InstRW<[V2Write_2cyc_1L01_1S_1V01], (instregex "^ST1H(_[SD])?$")>;
-def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BWD]$",
- "^ST1B_[HSD]$",
- "^ST1W_D$")>;
+def : InstRW<[V2Write_2c_1L01_1S_1V01], (instregex "^ST1H(_[SD])?$")>;
+def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BWD]$",
+ "^ST1B_[HSD]$",
+ "^ST1W_D$")>;
// Contiguous store two structures from two vectors, scalar + imm
-def : InstRW<[V2Write_4cyc_1L01_1V01], (instregex "^ST2[BHWD]_IMM$")>;
+def : InstRW<[V2Write_4c_1L01_1V01], (instregex "^ST2[BHWD]_IMM$")>;
// Contiguous store two structures from two vectors, scalar + scalar
-def : InstRW<[V2Write_4cyc_2L01_2S_2V01], (instrs ST2H)>;
-def : InstRW<[V2Write_4cyc_2L01_2V01], (instregex "^ST2[BWD]$")>;
+def : InstRW<[V2Write_4c_2L01_2S_2V01], (instrs ST2H)>;
+def : InstRW<[V2Write_4c_2L01_2V01], (instregex "^ST2[BWD]$")>;
// Contiguous store three structures from three vectors, scalar + imm
-def : InstRW<[V2Write_7cyc_9L01_9V01], (instregex "^ST3[BHWD]_IMM$")>;
+def : InstRW<[V2Write_7c_9L01_9V01], (instregex "^ST3[BHWD]_IMM$")>;
// Contiguous store three structures from three vectors, scalar + scalar
-def : InstRW<[V2Write_7cyc_9L01_9S_9V01], (instregex "^ST3[BHWD]$")>;
+def : InstRW<[V2Write_7c_9L01_9S_9V01], (instregex "^ST3[BHWD]$")>;
// Contiguous store four structures from four vectors, scalar + imm
-def : InstRW<[V2Write_11cyc_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>;
+def : InstRW<[V2Write_11c_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>;
// Contiguous store four structures from four vectors, scalar + scalar
-def : InstRW<[V2Write_11cyc_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>;
+def : InstRW<[V2Write_11c_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>;
// Non temporal store, scalar + imm
-def : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;
+def : InstRW<[V2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;
// Non temporal store, scalar + scalar
-def : InstRW<[V2Write_2cyc_1L01_1S_1V], (instrs STNT1H_ZRR)>;
-def : InstRW<[V2Write_2cyc_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>;
+def : InstRW<[V2Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>;
+def : InstRW<[V2Write_2c_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>;
// Scatter non temporal store, vector + scalar 32-bit element size
-def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>;
+def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>;
// Scatter non temporal store, vector + scalar 64-bit element size
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^STNT1[BHWD]_ZZR_D")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^STNT1[BHWD]_ZZR_D")>;
// Scatter store vector + imm 32-bit element size
-def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_IMM$",
- "^SST1W_IMM$")>;
+def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^SST1[BH]_S_IMM$",
+ "^SST1W_IMM$")>;
// Scatter store vector + imm 64-bit element size
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_IMM$",
- "^SST1D_IMM$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D_IMM$",
+ "^SST1D_IMM$")>;
// Scatter store, 32-bit scaled offset
-def : InstRW<[V2Write_4cyc_4L01_4V01],
+def : InstRW<[V2Write_4c_4L01_4V01],
(instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;
// Scatter store, 32-bit unpacked unscaled offset
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D_[SU]XTW$",
- "^SST1D_[SU]XTW$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D_[SU]XTW$",
+ "^SST1D_[SU]XTW$")>;
// Scatter store, 32-bit unpacked scaled offset
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
- "^SST1D_[SU]XTW_SCALED$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",
+ "^SST1D_[SU]XTW_SCALED$")>;
// Scatter store, 32-bit unscaled offset
-def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$",
- "^SST1W_[SU]XTW$")>;
+def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$",
+ "^SST1W_[SU]XTW$")>;
// Scatter store, 64-bit scaled offset
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[HW]_D_SCALED$",
- "^SST1D_SCALED$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[HW]_D_SCALED$",
+ "^SST1D_SCALED$")>;
// Scatter store, 64-bit unscaled offset
-def : InstRW<[V2Write_2cyc_2L01_2V01], (instregex "^SST1[BHW]_D$",
- "^SST1D$")>;
+def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D$",
+ "^SST1D$")>;
// SVE Miscellaneous instructions
// -----------------------------------------------------------------------------
// Read first fault register, unpredicated
-def : InstRW<[V2Write_2cyc_1M0], (instrs RDFFR_P)>;
+def : InstRW<[V2Write_2c_1M0], (instrs RDFFR_P)>;
// Read first fault register, predicated
-def : InstRW<[V2Write_3or4cyc_1M0_1M], (instrs RDFFR_PPz)>;
+def : InstRW<[V2Write_3or4c_1M0_1M], (instrs RDFFR_PPz)>;
// Read first fault register and set flags
-def : InstRW<[V2Write_4or5cyc_2M0_2M], (instrs RDFFRS_PPz)>;
+def : InstRW<[V2Write_4or5c_2M0_2M], (instrs RDFFRS_PPz)>;
// Set first fault register
// Write to first fault register
-def : InstRW<[V2Write_2cyc_1M0], (instrs SETFFR, WRFFR)>;
+def : InstRW<[V2Write_2c_1M0], (instrs SETFFR, WRFFR)>;
// Prefetch
// NOTE: This is not specified in the SOG.
-def : InstRW<[V2Write_4cyc_1L], (instregex "^PRF[BHWD]")>;
+def : InstRW<[V2Write_4c_1L], (instregex "^PRF[BHWD]")>;
// SVE Cryptographic instructions
// -----------------------------------------------------------------------------
// Crypto AES ops
-def : InstRW<[V2Write_2cyc_1V], (instregex "^AES[DE]_ZZZ_B$",
- "^AESI?MC_ZZ_B$")>;
+def : InstRW<[V2Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",
+ "^AESI?MC_ZZ_B$")>;
// Crypto SHA3 ops
-def : InstRW<[V2Write_2cyc_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",
- "^RAX1_ZZZ_D$",
- "^XAR_ZZZI_[BHSD]$")>;
+def : InstRW<[V2Write_2c_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",
+ "^RAX1_ZZZ_D$",
+ "^XAR_ZZZI_[BHSD]$")>;
// Crypto SM4 ops
-def : InstRW<[V2Write_4cyc_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
+def : InstRW<[V2Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
}
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