[llvm] [AMDGPU] Fix selection of s_load_b96 on GFX11 (PR #108029)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 05:40:01 PDT 2024
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/108029
>From ac3badde296cc4e1f873361c3f53b23edbd1699f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 10 Sep 2024 14:41:24 +0100
Subject: [PATCH 1/6] refactor
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 36 +++++++++++------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 736f714ac1a77c..77a024439d1e97 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10322,9 +10322,9 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
unsigned NumElements = MemVT.getVectorNumElements();
- if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
- AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
- if (!Op->isDivergent() && Alignment >= Align(4) && NumElements < 32) {
+ if (!Op->isDivergent() && Alignment >= Align(4) && NumElements < 32) {
+ if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
+ AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
if (MemVT.isPow2VectorType() ||
(Subtarget->hasScalarDwordx3Loads() && NumElements == 3))
return SDValue();
@@ -10334,24 +10334,24 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
// have the same legalization requirements as global and private
// loads.
//
- }
- if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
- AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
- AS == AMDGPUAS::GLOBAL_ADDRESS) {
- if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
- Load->isSimple() && isMemOpHasNoClobberedMemOperand(Load) &&
- Alignment >= Align(4) && NumElements < 32) {
- if (MemVT.isPow2VectorType() ||
- (Subtarget->hasScalarDwordx3Loads() && NumElements == 3))
- return SDValue();
- return WidenOrSplitVectorLoad(Op, DAG);
+ if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
+ AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
+ AS == AMDGPUAS::GLOBAL_ADDRESS) {
+ if (Subtarget->getScalarizeGlobalBehavior() && Load->isSimple() &&
+ isMemOpHasNoClobberedMemOperand(Load)) {
+ if (MemVT.isPow2VectorType() ||
+ (Subtarget->hasScalarDwordx3Loads() && NumElements == 3))
+ return SDValue();
+ return WidenOrSplitVectorLoad(Op, DAG);
+ }
+ // Non-uniform loads will be selected to MUBUF instructions, so they
+ // have the same legalization requirements as global and private
+ // loads.
+ //
}
- // Non-uniform loads will be selected to MUBUF instructions, so they
- // have the same legalization requirements as global and private
- // loads.
- //
}
+
if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
AS == AMDGPUAS::GLOBAL_ADDRESS ||
>From 90456361928754fd5ffaad05244e67a5e19ff7af Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 10 Sep 2024 14:44:35 +0100
Subject: [PATCH 2/6] fix bug
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 ++-
.../AMDGPU/load-constant-always-uniform.ll | 42 +++++++++++++++++++
2 files changed, 45 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 77a024439d1e97..8b2e47a0b1b921 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10256,6 +10256,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadSDNode *Load = cast<LoadSDNode>(Op);
ISD::LoadExtType ExtType = Load->getExtensionType();
EVT MemVT = Load->getMemoryVT();
+ MachineMemOperand *MMO = Load->getMemOperand();
if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
if (MemVT == MVT::i16 && isTypeLegal(MVT::i16))
@@ -10266,7 +10267,6 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Load->getChain();
SDValue BasePtr = Load->getBasePtr();
- MachineMemOperand *MMO = Load->getMemOperand();
EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
@@ -10322,7 +10322,8 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
unsigned NumElements = MemVT.getVectorNumElements();
- if (!Op->isDivergent() && Alignment >= Align(4) && NumElements < 32) {
+ if ((!Op->isDivergent() || AMDGPUInstrInfo::isUniformMMO(MMO)) &&
+ Alignment >= Align(4) && NumElements < 32) {
if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
if (MemVT.isPow2VectorType() ||
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
new file mode 100644
index 00000000000000..719a9e0ccb0144
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -prefix=GFX11
+
+define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-size"="1,1" {
+; CHECK-LABEL: test_uniform_load_b96:
+; CHECK: ; %bb.0: ; %bb
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; CHECK-NEXT: v_readfirstlane_b32 s1, v1
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
+; CHECK-NEXT: s_load_b32 s0, s[0:1], 0x8
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v2, s3
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_or3_b32 v2, s2, v2, s0
+; CHECK-NEXT: global_store_b32 v[0:1], v2, off
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; CHECK-NEXT: s_endpgm
+bb:
+ %i = zext i32 %arg to i64
+ %i1 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i
+ %i2 = load i32, ptr addrspace(1) %i1, align 4
+ %i3 = add nuw i32 %arg, 1
+ %i4 = zext i32 %i3 to i64
+ %i5 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i4
+ %i6 = load i32, ptr addrspace(1) %i5, align 4
+ %i7 = add nuw i32 %arg, 2
+ %i8 = zext i32 %i7 to i64
+ %i9 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i8
+ %i10 = load i32, ptr addrspace(1) %i9, align 4
+ %i11 = or i32 %i2, %i6
+ %i12 = or i32 %i10, %i11
+ store i32 %i12, ptr addrspace(1) null, align 4
+ ret void
+}
>From 9544c74387ba0e04a445f2a6137daefa451a55d4 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 11 Sep 2024 09:15:07 +0100
Subject: [PATCH 3/6] add GFX12 testing
---
.../AMDGPU/load-constant-always-uniform.ll | 65 ++++++++++++-------
1 file changed, 43 insertions(+), 22 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
index 719a9e0ccb0144..a40045f90d6fa5 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
@@ -1,28 +1,49 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -prefix=GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12
define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-size"="1,1" {
-; CHECK-LABEL: test_uniform_load_b96:
-; CHECK: ; %bb.0: ; %bb
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; CHECK-NEXT: v_readfirstlane_b32 s0, v0
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; CHECK-NEXT: v_readfirstlane_b32 s1, v1
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
-; CHECK-NEXT: s_load_b32 s0, s[0:1], 0x8
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v2, s3
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; CHECK-NEXT: v_or3_b32 v2, s2, v2, s0
-; CHECK-NEXT: global_store_b32 v[0:1], v2, off
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; CHECK-NEXT: s_endpgm
+; GFX11-LABEL: test_uniform_load_b96:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x8
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or3_b32 v2, s2, v2, s0
+; GFX11-NEXT: global_store_b32 v[0:1], v2, off
+; GFX11-NEXT: s_nop 0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: test_uniform_load_b96:
+; GFX12: ; %bb.0: ; %bb
+; GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_or3_b32 v2, v2, s1, s2
+; GFX12-NEXT: global_store_b32 v[0:1], v2, off
+; GFX12-NEXT: s_nop 0
+; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT: s_endpgm
bb:
%i = zext i32 %arg to i64
%i1 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i
>From e535023d87ee980893cf2bd60d85d4521867062c Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 11 Sep 2024 09:22:21 +0100
Subject: [PATCH 4/6] more nfc commoning and refactoring
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 28 ++++++-----------------
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 8b2e47a0b1b921..805ae12b2b4dd5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10322,10 +10322,13 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
unsigned NumElements = MemVT.getVectorNumElements();
- if ((!Op->isDivergent() || AMDGPUInstrInfo::isUniformMMO(MMO)) &&
- Alignment >= Align(4) && NumElements < 32) {
- if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
- AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
+ if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
+ AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
+ (AS == AMDGPUAS::GLOBAL_ADDRESS &&
+ Subtarget->getScalarizeGlobalBehavior() && Load->isSimple() &&
+ isMemOpHasNoClobberedMemOperand(Load))) {
+ if ((!Op->isDivergent() || AMDGPUInstrInfo::isUniformMMO(MMO)) &&
+ Alignment >= Align(4) && NumElements < 32) {
if (MemVT.isPow2VectorType() ||
(Subtarget->hasScalarDwordx3Loads() && NumElements == 3))
return SDValue();
@@ -10335,24 +10338,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
// have the same legalization requirements as global and private
// loads.
//
-
- if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
- AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
- AS == AMDGPUAS::GLOBAL_ADDRESS) {
- if (Subtarget->getScalarizeGlobalBehavior() && Load->isSimple() &&
- isMemOpHasNoClobberedMemOperand(Load)) {
- if (MemVT.isPow2VectorType() ||
- (Subtarget->hasScalarDwordx3Loads() && NumElements == 3))
- return SDValue();
- return WidenOrSplitVectorLoad(Op, DAG);
- }
- // Non-uniform loads will be selected to MUBUF instructions, so they
- // have the same legalization requirements as global and private
- // loads.
- //
- }
}
-
if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
AS == AMDGPUAS::GLOBAL_ADDRESS ||
>From aa0728ba3704e3a927d59afdef7b8517a43694b6 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 11 Sep 2024 12:21:49 +0100
Subject: [PATCH 5/6] simplify IR in test
---
.../AMDGPU/load-constant-always-uniform.ll | 21 +++++++------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
index a40045f90d6fa5..b7dc8dc7900382 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
@@ -46,18 +46,13 @@ define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-s
; GFX12-NEXT: s_endpgm
bb:
%i = zext i32 %arg to i64
- %i1 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i
- %i2 = load i32, ptr addrspace(1) %i1, align 4
- %i3 = add nuw i32 %arg, 1
- %i4 = zext i32 %i3 to i64
- %i5 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i4
- %i6 = load i32, ptr addrspace(1) %i5, align 4
- %i7 = add nuw i32 %arg, 2
- %i8 = zext i32 %i7 to i64
- %i9 = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(1) null, i64 0, i32 0, i64 %i8
- %i10 = load i32, ptr addrspace(1) %i9, align 4
- %i11 = or i32 %i2, %i6
- %i12 = or i32 %i10, %i11
- store i32 %i12, ptr addrspace(1) null, align 4
+ %i1 = getelementptr i32, ptr addrspace(1) null, i64 %i
+ %i2 = load <3 x i32>, ptr addrspace(1) %i1, align 4
+ %i3 = extractelement <3 x i32> %i2, i32 0
+ %i4 = extractelement <3 x i32> %i2, i32 1
+ %i5 = extractelement <3 x i32> %i2, i32 2
+ %i6 = or i32 %i3, %i4
+ %i7 = or i32 %i5, %i6
+ store i32 %i7, ptr addrspace(1) null, align 4
ret void
}
>From 80993c6a6e9fef20dc8b2e9b764405c300d28c4a Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Thu, 12 Sep 2024 13:38:34 +0100
Subject: [PATCH 6/6] use non-null pointer in test
---
.../AMDGPU/load-constant-always-uniform.ll | 34 ++++++++++---------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
index b7dc8dc7900382..668ebe3f953b32 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
@@ -2,17 +2,18 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GFX11
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12
-define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-size"="1,1" {
+define amdgpu_cs void @test_uniform_load_b96(ptr addrspace(1) %ptr, i32 %arg) "amdgpu-flat-work-group-size"="1,1" {
; GFX11-LABEL: test_uniform_load_b96:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
+; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s1, v1
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x8
@@ -27,14 +28,15 @@ define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-s
;
; GFX12-LABEL: test_uniform_load_b96:
; GFX12: ; %bb.0: ; %bb
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-NEXT: v_mov_b32_e32 v3, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
-; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
+; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
+; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v2, s0
@@ -46,13 +48,13 @@ define amdgpu_cs void @test_uniform_load_b96(i32 %arg) "amdgpu-flat-work-group-s
; GFX12-NEXT: s_endpgm
bb:
%i = zext i32 %arg to i64
- %i1 = getelementptr i32, ptr addrspace(1) null, i64 %i
+ %i1 = getelementptr i32, ptr addrspace(1) %ptr, i64 %i
%i2 = load <3 x i32>, ptr addrspace(1) %i1, align 4
%i3 = extractelement <3 x i32> %i2, i32 0
%i4 = extractelement <3 x i32> %i2, i32 1
%i5 = extractelement <3 x i32> %i2, i32 2
%i6 = or i32 %i3, %i4
%i7 = or i32 %i5, %i6
- store i32 %i7, ptr addrspace(1) null, align 4
+ store i32 %i7, ptr addrspace(1) %ptr, align 4
ret void
}
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