[llvm] [InitUndef] Enable the InitUndef pass on all targets (PR #108353)

[Piyou Chen via llvm-commits]

BeMg wrote:

> The AMDGPU usage is a very literal interpretation of what "early clobber" means, i.e. (some part of) the output might get written before (some parts of) the inputs are read.
> 
> For the architectural constraints in ARM and RISCV, is the output forbidden from overlapping with any input, or with one specific input? If the latter, maybe a better way to model it would be with something like `Constraints = "$dst != $src2"` in the tablegen definition of the instruction -- but that would require support in all register allocators, and I don't know how much effort anyone wants to put into better handling for this minor codegen issue.

In RISC-V, we are trying to resolve a case involving the `vrgather.vv` instruction by InitUndef, where the destination register cannot overlap with any source register; otherwise, it is considered an illegal instruction.


https://github.com/llvm/llvm-project/pull/108353