[llvm] a71407e - [AArch64] Regenerate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 02:21:35 PDT 2024
Author: Nikita Popov
Date: 2024-09-12T11:21:27+02:00
New Revision: a71407ed3a5f11e9f7ab2060f2557384c643eff4
URL: https://github.com/llvm/llvm-project/commit/a71407ed3a5f11e9f7ab2060f2557384c643eff4
DIFF: https://github.com/llvm/llvm-project/commit/a71407ed3a5f11e9f7ab2060f2557384c643eff4.diff
LOG: [AArch64] Regenerate test checks (NFC)
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll b/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
index 99f2ff04984e3c..0153505250d6fb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
@@ -1,11 +1,14 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=1 -pass-remarks-missed=gisel* -mtriple=arm64-linux-gnu 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefixes=CHECK,SDAG
+; RUN: llc < %s -global-isel -global-isel-abort=1 -pass-remarks-missed=gisel* -mtriple=arm64-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL,FALLBACK
%0 = type { i64, i64 }
define dso_local i128 @f0(ptr %p) nounwind readonly {
; CHECK-LABEL: f0:
-; CHECK: ldxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldxp x0, x1, [x0]
+; CHECK-NEXT: ret
entry:
%ldrexd = tail call %0 @llvm.aarch64.ldxp(ptr %p)
%0 = extractvalue %0 %ldrexd, 1
@@ -19,7 +22,10 @@ entry:
define dso_local i32 @f1(ptr %ptr, i128 %val) nounwind {
; CHECK-LABEL: f1:
-; CHECK: stxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stxp w8, x2, x3, [x0]
+; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ret
entry:
%tmp4 = trunc i128 %val to i64
%tmp6 = lshr i128 %val, 64
@@ -35,16 +41,21 @@ declare i32 @llvm.aarch64.stxp(i64, i64, ptr) nounwind
; FALLBACK-NOT: remark:{{.*}}test_load_i8
define dso_local void @test_load_i8(ptr %addr) {
-; CHECK-LABEL: test_load_i8:
-; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_i8:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldxrb w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_i8:
-; GISEL: ldxrb w[[LOADVAL:[0-9]+]], [x0]
-; GISEL-NOT: uxtb
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldxrb w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: and x9, x9, #0xff
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i8) %addr)
%shortval = trunc i64 %val to i8
%extval = zext i8 %shortval to i64
@@ -54,16 +65,21 @@ define dso_local void @test_load_i8(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_i16
define dso_local void @test_load_i16(ptr %addr) {
-; CHECK-LABEL: test_load_i16:
-; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_i16:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldxrh w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_i16:
-; GISEL: ldxrh w[[LOADVAL:[0-9]+]], [x0]
-; GISEL-NOT: uxtb
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldxrh w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: and x9, x9, #0xffff
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i16) %addr)
%shortval = trunc i64 %val to i16
%extval = zext i16 %shortval to i64
@@ -73,16 +89,21 @@ define dso_local void @test_load_i16(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_i32
define dso_local void @test_load_i32(ptr %addr) {
-; CHECK-LABEL: test_load_i32:
-; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_i32:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldxr w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_i32:
-; GISEL: ldxr w[[LOADVAL:[0-9]+]], [x0]
-; GISEL-NOT: uxtb
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldxr w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: mov w9, w9
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)
%shortval = trunc i64 %val to i32
%extval = zext i32 %shortval to i64
@@ -93,13 +114,12 @@ define dso_local void @test_load_i32(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_i64
define dso_local void @test_load_i64(ptr %addr) {
; CHECK-LABEL: test_load_i64:
-; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldxr x8, [x0]
+; CHECK-NEXT: adrp x9, var
+; CHECK-NEXT: str x8, [x9, :lo12:var]
+; CHECK-NEXT: ret
-; GISEL-LABEL: test_load_i64:
-; GISEL: ldxr x[[LOADVAL:[0-9]+]], [x0]
-; GISEL-NOT: uxtb
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i64) %addr)
store i64 %val, ptr @var, align 8
ret void
@@ -111,13 +131,10 @@ declare i64 @llvm.aarch64.ldxr.p0(ptr) nounwind
; FALLBACK-NOT: remark:{{.*}}test_store_i8
define dso_local i32 @test_store_i8(i32, i8 %val, ptr %addr) {
; CHECK-LABEL: test_store_i8:
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: stxrb w0, w1, [x2]
-; GISEL-LABEL: test_store_i8:
-; GISEL-NOT: uxtb
-; GISEL-NOT: and
-; GISEL: stxrb w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: stxrb w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i8 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i8) %addr)
ret i32 %res
@@ -126,13 +143,10 @@ define dso_local i32 @test_store_i8(i32, i8 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_i16
define dso_local i32 @test_store_i16(i32, i16 %val, ptr %addr) {
; CHECK-LABEL: test_store_i16:
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: stxrh w0, w1, [x2]
-; GISEL-LABEL: test_store_i16:
-; GISEL-NOT: uxth
-; GISEL-NOT: and
-; GISEL: stxrh w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: stxrh w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i16 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i16) %addr)
ret i32 %res
@@ -141,13 +155,9 @@ define dso_local i32 @test_store_i16(i32, i16 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_i32
define dso_local i32 @test_store_i32(i32, i32 %val, ptr %addr) {
; CHECK-LABEL: test_store_i32:
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: stxr w0, w1, [x2]
-; GISEL-LABEL: test_store_i32:
-; GISEL-NOT: uxtw
-; GISEL-NOT: and
-; GISEL: stxr w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stxr w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i32 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i32) %addr)
ret i32 %res
@@ -156,18 +166,20 @@ define dso_local i32 @test_store_i32(i32, i32 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_i64
define dso_local i32 @test_store_i64(i32, i64 %val, ptr %addr) {
; CHECK-LABEL: test_store_i64:
-; CHECK: stxr w0, x1, [x2]
-; GISEL-LABEL: test_store_i64:
-; GISEL: stxr w0, x1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stxr w0, x1, [x2]
+; CHECK-NEXT: ret
%res = call i32 @llvm.aarch64.stxr.p0(i64 %val, ptr elementtype(i64) %addr)
ret i32 %res
}
declare i32 @llvm.aarch64.stxr.p0(i64, ptr) nounwind
-; CHECK: test_clear:
-; CHECK: clrex
define dso_local void @test_clear() {
+; CHECK-LABEL: test_clear:
+; CHECK: // %bb.0:
+; CHECK-NEXT: clrex
+; CHECK-NEXT: ret
call void @llvm.aarch64.clrex()
ret void
}
@@ -176,7 +188,9 @@ declare void @llvm.aarch64.clrex() nounwind
define dso_local i128 @test_load_acquire_i128(ptr %p) nounwind readonly {
; CHECK-LABEL: test_load_acquire_i128:
-; CHECK: ldaxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldaxp x0, x1, [x0]
+; CHECK-NEXT: ret
entry:
%ldrexd = tail call %0 @llvm.aarch64.ldaxp(ptr %p)
%0 = extractvalue %0 %ldrexd, 1
@@ -190,7 +204,10 @@ entry:
define dso_local i32 @test_store_release_i128(ptr %ptr, i128 %val) nounwind {
; CHECK-LABEL: test_store_release_i128:
-; CHECK: stlxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stlxp w8, x2, x3, [x0]
+; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ret
entry:
%tmp4 = trunc i128 %val to i64
%tmp6 = lshr i128 %val, 64
@@ -204,15 +221,21 @@ declare i32 @llvm.aarch64.stlxp(i64, i64, ptr) nounwind
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i8
define dso_local void @test_load_acquire_i8(ptr %addr) {
-; CHECK-LABEL: test_load_acquire_i8:
-; CHECK: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_acquire_i8:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldaxrb w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_acquire_i8:
-; GISEL: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
-; GISEL-DAG: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldaxrb w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: and x9, x9, #0xff
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i8) %addr)
%shortval = trunc i64 %val to i8
%extval = zext i8 %shortval to i64
@@ -222,15 +245,21 @@ define dso_local void @test_load_acquire_i8(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i16
define dso_local void @test_load_acquire_i16(ptr %addr) {
-; CHECK-LABEL: test_load_acquire_i16:
-; CHECK: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_acquire_i16:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldaxrh w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_acquire_i16:
-; GISEL: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldaxrh w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: and x9, x9, #0xffff
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) %addr)
%shortval = trunc i64 %val to i16
%extval = zext i16 %shortval to i64
@@ -240,15 +269,21 @@ define dso_local void @test_load_acquire_i16(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i32
define dso_local void @test_load_acquire_i32(ptr %addr) {
-; CHECK-LABEL: test_load_acquire_i32:
-; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
+; SDAG-LABEL: test_load_acquire_i32:
+; SDAG: // %bb.0:
+; SDAG-NEXT: ldaxr w8, [x0]
+; SDAG-NEXT: adrp x9, var
+; SDAG-NEXT: str x8, [x9, :lo12:var]
+; SDAG-NEXT: ret
+;
; GISEL-LABEL: test_load_acquire_i32:
-; GISEL: ldaxr w[[LOADVAL:[0-9]+]], [x0]
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL: // %bb.0:
+; GISEL-NEXT: ldaxr w9, [x0]
+; GISEL-NEXT: adrp x8, var
+; GISEL-NEXT: mov w9, w9
+; GISEL-NEXT: str x9, [x8, :lo12:var]
+; GISEL-NEXT: ret
+
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) %addr)
%shortval = trunc i64 %val to i32
%extval = zext i32 %shortval to i64
@@ -259,12 +294,12 @@ define dso_local void @test_load_acquire_i32(ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i64
define dso_local void @test_load_acquire_i64(ptr %addr) {
; CHECK-LABEL: test_load_acquire_i64:
-; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldaxr x8, [x0]
+; CHECK-NEXT: adrp x9, var
+; CHECK-NEXT: str x8, [x9, :lo12:var]
+; CHECK-NEXT: ret
-; GISEL-LABEL: test_load_acquire_i64:
-; GISEL: ldaxr x[[LOADVAL:[0-9]+]], [x0]
-; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i64) %addr)
store i64 %val, ptr @var, align 8
ret void
@@ -276,13 +311,10 @@ declare i64 @llvm.aarch64.ldaxr.p0(ptr) nounwind
; FALLBACK-NOT: remark:{{.*}}test_store_release_i8
define dso_local i32 @test_store_release_i8(i32, i8 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i8:
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: stlxrb w0, w1, [x2]
-; GISEL-LABEL: test_store_release_i8:
-; GISEL-NOT: uxtb
-; GISEL-NOT: and
-; GISEL: stlxrb w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: stlxrb w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i8 %val to i64
%res = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i8) %addr)
ret i32 %res
@@ -291,13 +323,10 @@ define dso_local i32 @test_store_release_i8(i32, i8 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_release_i16
define dso_local i32 @test_store_release_i16(i32, i16 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i16:
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: stlxrh w0, w1, [x2]
-; GISEL-LABEL: test_store_release_i16:
-; GISEL-NOT: uxth
-; GISEL-NOT: and
-; GISEL: stlxrh w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: stlxrh w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i16 %val to i64
%res = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i16) %addr)
ret i32 %res
@@ -306,13 +335,9 @@ define dso_local i32 @test_store_release_i16(i32, i16 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_release_i32
define dso_local i32 @test_store_release_i32(i32, i32 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i32:
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: stlxr w0, w1, [x2]
-; GISEL-LABEL: test_store_release_i32:
-; GISEL-NOT: uxtw
-; GISEL-NOT: and
-; GISEL: stlxr w0, w1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stlxr w0, w1, [x2]
+; CHECK-NEXT: ret
%extval = zext i32 %val to i64
%res = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i32) %addr)
ret i32 %res
@@ -321,11 +346,13 @@ define dso_local i32 @test_store_release_i32(i32, i32 %val, ptr %addr) {
; FALLBACK-NOT: remark:{{.*}}test_store_release_i64
define dso_local i32 @test_store_release_i64(i32, i64 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i64:
-; CHECK: stlxr w0, x1, [x2]
-; GISEL-LABEL: test_store_release_i64:
-; GISEL: stlxr w0, x1, [x2]
+; CHECK: // %bb.0:
+; CHECK-NEXT: stlxr w0, x1, [x2]
+; CHECK-NEXT: ret
%res = call i32 @llvm.aarch64.stlxr.p0(i64 %val, ptr elementtype(i64) %addr)
ret i32 %res
}
declare i32 @llvm.aarch64.stlxr.p0(i64, ptr) nounwind
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; FALLBACK: {{.*}}
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