[llvm] [RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (PR #108338)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 00:25:00 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
This handles int->fp/fp->int nodes for zvfbfmin, reusing the same parts that f16 uses with zvfhmin.
There's quite a bit of replication here that can probably be cleaned up at some point.
---
Patch is 104.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108338.diff
11 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+33-22)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll (+730-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll (+30-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll (+124-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll (+30-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll (+124-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll (+718-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll (+31-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll (+134-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll (+31-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll (+126-12)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 682bdc7071bc42..590f872dc15bf5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1114,6 +1114,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
+ setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP,
+ ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
+ VT, Custom);
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
ISD::EXTRACT_SUBVECTOR},
VT, Custom);
@@ -6659,17 +6662,19 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
if (Op.getValueType().isVector() &&
- Op.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) {
- if (Op.getValueType() == MVT::nxv32f16)
+ ((Op.getValueType().getScalarType() == MVT::f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16())) ||
+ Op.getValueType().getScalarType() == MVT::bf16)) {
+ if (Op.getValueType() == MVT::nxv32f16 ||
+ Op.getValueType() == MVT::nxv32bf16)
return SplitVectorOp(Op, DAG);
// int -> f32
SDLoc DL(Op);
MVT NVT =
MVT::getVectorVT(MVT::f32, Op.getValueType().getVectorElementCount());
SDValue NC = DAG.getNode(Op.getOpcode(), DL, NVT, Op->ops());
- // f32 -> f16
+ // f32 -> [b]f16
return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NC,
DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
}
@@ -6678,12 +6683,14 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::FP_TO_UINT:
if (SDValue Op1 = Op.getOperand(0);
Op1.getValueType().isVector() &&
- Op1.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) {
- if (Op1.getValueType() == MVT::nxv32f16)
+ ((Op1.getValueType().getScalarType() == MVT::f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16())) ||
+ Op1.getValueType().getScalarType() == MVT::bf16)) {
+ if (Op1.getValueType() == MVT::nxv32f16 ||
+ Op1.getValueType() == MVT::nxv32bf16)
return SplitVectorOp(Op, DAG);
- // f16 -> f32
+ // [b]f16 -> f32
SDLoc DL(Op);
MVT NVT = MVT::getVectorVT(MVT::f32,
Op1.getValueType().getVectorElementCount());
@@ -7394,17 +7401,19 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_SINT_TO_FP:
case ISD::VP_UINT_TO_FP:
if (Op.getValueType().isVector() &&
- Op.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) {
- if (Op.getValueType() == MVT::nxv32f16)
- return SplitVPOp(Op, DAG);
+ ((Op.getValueType().getScalarType() == MVT::f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16())) ||
+ Op.getValueType().getScalarType() == MVT::bf16)) {
+ if (Op.getValueType() == MVT::nxv32f16 ||
+ Op.getValueType() == MVT::nxv32bf16)
+ return SplitVectorOp(Op, DAG);
// int -> f32
SDLoc DL(Op);
MVT NVT =
MVT::getVectorVT(MVT::f32, Op.getValueType().getVectorElementCount());
auto NC = DAG.getNode(Op.getOpcode(), DL, NVT, Op->ops());
- // f32 -> f16
+ // f32 -> [b]f16
return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NC,
DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
}
@@ -7413,12 +7422,14 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_FP_TO_UINT:
if (SDValue Op1 = Op.getOperand(0);
Op1.getValueType().isVector() &&
- Op1.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) {
- if (Op1.getValueType() == MVT::nxv32f16)
- return SplitVPOp(Op, DAG);
- // f16 -> f32
+ ((Op1.getValueType().getScalarType() == MVT::f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16())) ||
+ Op1.getValueType().getScalarType() == MVT::bf16)) {
+ if (Op1.getValueType() == MVT::nxv32f16 ||
+ Op1.getValueType() == MVT::nxv32bf16)
+ return SplitVectorOp(Op, DAG);
+ // [b]f16 -> f32
SDLoc DL(Op);
MVT NVT = MVT::getVectorVT(MVT::f32,
Op1.getValueType().getVectorElementCount());
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
index b888fde7d06836..4edaa3825e5879 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
@@ -1,12 +1,734 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN
+
+define <vscale x 1 x i1> @vfptosi_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
+ ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i7> @vfptosi_nxv1bf16_nxv1i7(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i7>
+ ret <vscale x 1 x i7> %evec
+}
+
+define <vscale x 1 x i7> @vfptoui_nxv1bf16_nxv1i7(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i7>
+ ret <vscale x 1 x i7> %evec
+}
+
+define <vscale x 1 x i1> @vfptoui_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
+ ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i8> @vfptosi_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i8>
+ ret <vscale x 1 x i8> %evec
+}
+
+define <vscale x 1 x i8> @vfptoui_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i8>
+ ret <vscale x 1 x i8> %evec
+}
+
+define <vscale x 1 x i16> @vfptosi_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i16>
+ ret <vscale x 1 x i16> %evec
+}
+
+define <vscale x 1 x i16> @vfptoui_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i16>
+ ret <vscale x 1 x i16> %evec
+}
+
+define <vscale x 1 x i32> @vfptosi_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %evec
+}
+
+define <vscale x 1 x i32> @vfptoui_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %evec
+}
+
+define <vscale x 1 x i64> @vfptosi_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i64>
+ ret <vscale x 1 x i64> %evec
+}
+
+define <vscale x 1 x i64> @vfptoui_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i64>
+ ret <vscale x 1 x i64> %evec
+}
+
+define <vscale x 2 x i1> @vfptosi_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
+ ret <vscale x 2 x i1> %evec
+}
+
+define <vscale x 2 x i1> @vfptoui_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
+ ret <vscale x 2 x i1> %evec
+}
+
+define <vscale x 2 x i8> @vfptosi_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i8>
+ ret <vscale x 2 x i8> %evec
+}
+
+define <vscale x 2 x i8> @vfptoui_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i8>
+ ret <vscale x 2 x i8> %evec
+}
+
+define <vscale x 2 x i16> @vfptosi_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i16>
+ ret <vscale x 2 x i16> %evec
+}
+
+define <vscale x 2 x i16> @vfptoui_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i16>
+ ret <vscale x 2 x i16> %evec
+}
+
+define <vscale x 2 x i32> @vfptosi_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %evec
+}
+
+define <vscale x 2 x i32> @vfptoui_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %evec
+}
+
+define <vscale x 2 x i64> @vfptosi_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i64>
+ ret <vscale x 2 x i64> %evec
+}
+
+define <vscale x 2 x i64> @vfptoui_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i64>
+ ret <vscale x 2 x i64> %evec
+}
+
+define <vscale x 4 x i1> @vfptosi_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
+ ret <vscale x 4 x i1> %evec
+}
+
+define <vscale x 4 x i1> @vfptoui_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
+ ret <vscale x 4 x i1> %evec
+}
+
+define <vscale x 4 x i8> @vfptosi_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i8>
+ ret <vscale x 4 x i8> %evec
+}
+
+define <vscale x 4 x i8> @vfptoui_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i8>
+ ret <vscale x 4 x i8> %evec
+}
+
+define <vscale x 4 x i16> @vfptosi_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i16>
+ ret <vscale x 4 x i16> %evec
+}
+
+define <vscale x 4 x i16> @vfptoui_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; CHECK-NEXT: ret
+ %evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i16>
+ ret <vscale x 4 x i16> %evec
+}
+
+define <vscale x 4 x i32> @vfptosi_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10
+; CHECK-NEXT: ret
+ %evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %evec
+}
+
+define <vscale x 4 x i32> @vfptoui_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %va) {
+; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i32:
+; CHE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/108338
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