[llvm] [AMDGPU] Avoid unneeded waitcounts before spill stores (PR #108303)

[Matt Arsenault via llvm-commits]

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@@ -901,7 +901,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
     }
   } else /* LGKM_CNT || EXP_CNT || VS_CNT || NUM_INST_CNTS */ {
     // Match the score to the destination registers.
-    for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
+    for (unsigned I = 0, E = Inst.getNumExplicitOperands(); I != E; ++I) {
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arsenm wrote:

I can never remember how all of these counts work with the 2 notions of "implicit". Does this catch the implicit-def present in the instruction definition? e.g. implicit-def $vcc on v_cmp_*

https://github.com/llvm/llvm-project/pull/108303