[llvm] [X86][AVX10.2] Support AVX10.2-COMEF new instructions. (PR #108063)

[via llvm-commits]

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@@ -26060,32 +26060,67 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
       if (CC == ISD::SETLT || CC == ISD::SETLE)
         std::swap(LHS, RHS);
 
-      SDValue Comi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
+      // For AVX10.2, Support EQ and NE
+      bool HasAVX10_2_COMX =
+          Subtarget.hasAVX10_2() && (CC == ISD::SETEQ || CC == ISD::SETNE);
+
+      // AVX10.2 COMPARE supports only v2f64, v4f32 or v8f16
+      auto SVT = LHS.getSimpleValueType();
+      bool HasAVX10_2_COMX_Ty =
+          (SVT == MVT::v2f64) || (SVT == MVT::v4f32) || (SVT == MVT::v8f16);
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mahesh-attarde wrote:

This check serves two purpose. 
1. Addresses limitation of VVOMX to SS,SH and SD. 
2. For other Datatype it falls back to original VCOMI sequence.

In absence of this, test_int_x86_avx10_maskz_max_nepbf16_128 from comi-flags.ll fails to select
```
LLVM ERROR: Cannot select: t13: i32 = X86ISD::COMX t5, t6
  t5: v8bf16 = bitcast t2
    t2: v8f16,ch = CopyFromReg t0, Register:v8f16 %0
      t1: v8f16 = Register %0
  t6: v8bf16 = bitcast t4
    t4: v8f16,ch = CopyFromReg t0, Register:v8f16 %1
      t3: v8f16 = Register %1
In function: test_x86_avx10_com_nesbf16_eq
```
so we need to keep this check and not use assertion.

https://github.com/llvm/llvm-project/pull/108063