[llvm] 30fbfe5 - [RISCV] Reorder zvfbfmin operation actions to match zvfhmin. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 11 09:13:55 PDT 2024
Author: Luke Lau
Date: 2024-09-12T00:13:40+08:00
New Revision: 30fbfe577efd0f70cf3d745d7d89170666239d67
URL: https://github.com/llvm/llvm-project/commit/30fbfe577efd0f70cf3d745d7d89170666239d67
DIFF: https://github.com/llvm/llvm-project/commit/30fbfe577efd0f70cf3d745d7d89170666239d67.diff
LOG: [RISCV] Reorder zvfbfmin operation actions to match zvfhmin. NFC
This makes it slightly easier to see what's different between the two.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d2e62579bbddfc..4554163d4551dc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1106,18 +1106,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (!isTypeLegal(VT))
continue;
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
Custom);
+ setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+ setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
+ Custom);
+ setOperationAction(ISD::SELECT_CC, VT, Expand);
setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
ISD::EXTRACT_SUBVECTOR},
VT, Custom);
- setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
if (Subtarget.hasStdExtZfbfmin())
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
- setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
- Custom);
- setOperationAction(ISD::SELECT_CC, VT, Expand);
+ setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
// TODO: Promote to fp32.
}
}
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