[llvm] 7c6592f - [TableGen] Change CodeGenRegister to use const Record pointer (#108027)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 11 08:53:50 PDT 2024
Author: Rahul Joshi
Date: 2024-09-11T08:53:47-07:00
New Revision: 7c6592f5a368e17c2b15469042c33a4e1cb7a0ff
URL: https://github.com/llvm/llvm-project/commit/7c6592f5a368e17c2b15469042c33a4e1cb7a0ff
DIFF: https://github.com/llvm/llvm-project/commit/7c6592f5a368e17c2b15469042c33a4e1cb7a0ff.diff
LOG: [TableGen] Change CodeGenRegister to use const Record pointer (#108027)
Change CodeGenRegister to use const Record pointer.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Added:
Modified:
llvm/utils/TableGen/AsmMatcherEmitter.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.h
llvm/utils/TableGen/Common/InfoByHwMode.cpp
llvm/utils/TableGen/Common/InfoByHwMode.h
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index e4ce0f89fd8da1..ef5186451b9eae 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1338,7 +1338,7 @@ void AsmMatcherInfo::buildRegisterClasses(
// Name the register classes which correspond to a user defined RegisterClass.
for (const CodeGenRegisterClass &RC : RegClassList) {
// Def will be NULL for non-user defined register classes.
- Record *Def = RC.getDef();
+ const Record *Def = RC.getDef();
if (!Def)
continue;
ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index cadc2429f47502..5b43f7dfa7ce78 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -34,7 +34,6 @@
#include <iterator>
#include <map>
#include <queue>
-#include <set>
#include <string>
#include <tuple>
#include <utility>
@@ -48,7 +47,7 @@ using namespace llvm;
// CodeGenSubRegIndex
//===----------------------------------------------------------------------===//
-CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum,
+CodeGenSubRegIndex::CodeGenSubRegIndex(const Record *R, unsigned Enum,
const CodeGenHwModes &CGH)
: TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
Name = std::string(R->getName());
@@ -99,7 +98,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
PrintFatalError(TheDef->getLoc(),
"CoveredBySubRegs must have two or more entries");
SmallVector<CodeGenSubRegIndex *, 8> IdxParts;
- for (Record *Part : Parts)
+ for (const Record *Part : Parts)
IdxParts.push_back(RegBank.getSubRegIdx(Part));
setConcatenationOf(IdxParts);
}
@@ -190,8 +189,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
// Add ad hoc alias links. This is a symmetric relationship between two
// registers, so build a symmetric graph by adding links in both ends.
- std::vector<Record *> Aliases = TheDef->getValueAsListOfDefs("Aliases");
- for (Record *Alias : Aliases) {
+ for (const Record *Alias : TheDef->getValueAsListOfDefs("Aliases")) {
CodeGenRegister *Reg = RegBank.getReg(Alias);
ExplicitAliases.push_back(Reg);
Reg->ExplicitAliases.push_back(this);
@@ -757,7 +755,8 @@ static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
M.erase(llvm::unique(M, deref<std::equal_to<>>()), M.end());
}
-CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
+CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
+ const Record *R)
: TheDef(R), Name(std::string(R->getName())),
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) {
GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
@@ -765,7 +764,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
if (TypeList.empty())
PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
- Record *Type = TypeList[i];
+ const Record *Type = TypeList[i];
if (!Type->isSubClassOf("ValueType"))
PrintFatalError(R->getLoc(),
"RegTypes list member '" + Type->getName() +
@@ -1168,9 +1167,9 @@ void CodeGenRegisterClass::buildRegUnitSet(
//===----------------------------------------------------------------------===//
CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank,
- Record *R)
+ const Record *R)
: TheDef(R), Name(std::string(R->getName())) {
- for (Record *RegClass : R->getValueAsListOfDefs("Classes"))
+ for (const Record *RegClass : R->getValueAsListOfDefs("Classes"))
Classes.push_back(RegBank.getRegClass(RegClass));
}
@@ -1178,7 +1177,7 @@ CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank,
// CodeGenRegBank
//===----------------------------------------------------------------------===//
-CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
+CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records,
const CodeGenHwModes &Modes)
: CGH(Modes) {
// Configure register Sets to understand register classes and tuples.
@@ -1189,10 +1188,8 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
// Read in the user-defined (named) sub-register indices.
// More indices will be synthesized later.
- std::vector<Record *> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
- llvm::sort(SRIs, LessRecord());
- for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
- getSubRegIdx(SRIs[i]);
+ for (const Record *SRI : Records.getAllDerivedDefinitions("SubRegIndex"))
+ getSubRegIdx(SRI);
// Build composite maps from ComposedOf fields.
for (auto &Idx : SubRegIndices)
Idx.updateComponents(*this);
@@ -1223,7 +1220,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
getReg(Regs[i]);
// Expand tuples and number the new registers.
- for (Record *R : Records.getAllDerivedDefinitions("RegisterTuples")) {
+ for (const Record *R : Records.getAllDerivedDefinitions("RegisterTuples")) {
std::vector<const Record *> TupRegs = *Sets.expand(R);
llvm::sort(TupRegs, LessRecordRegister());
for (const Record *RC : TupRegs)
@@ -1288,7 +1285,8 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
NumNativeRegUnits = RegUnits.size();
// Read in register class definitions.
- std::vector<Record *> RCs = Records.getAllDerivedDefinitions("RegisterClass");
+ ArrayRef<const Record *> RCs =
+ Records.getAllDerivedDefinitions("RegisterClass");
if (RCs.empty())
PrintFatalError("No 'RegisterClass' subclasses defined!");
@@ -1311,9 +1309,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
CodeGenRegisterClass::computeSubClasses(*this);
// Read in the register category definitions.
- std::vector<Record *> RCats =
- Records.getAllDerivedDefinitions("RegisterCategory");
- for (auto *R : RCats)
+ for (const Record *R : Records.getAllDerivedDefinitions("RegisterCategory"))
RegCategories.emplace_back(*this, R);
}
@@ -1324,7 +1320,7 @@ CodeGenSubRegIndex *CodeGenRegBank::createSubRegIndex(StringRef Name,
return &SubRegIndices.back();
}
-CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
+CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(const Record *Def) {
CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
if (Idx)
return Idx;
@@ -2450,7 +2446,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() {
/// return null. If the register is in multiple classes, and the classes have a
/// superset-subset relationship and the same set of types, return the
/// superclass. Otherwise return null.
-const CodeGenRegisterClass *CodeGenRegBank::getRegClassForRegister(Record *R) {
+const CodeGenRegisterClass *
+CodeGenRegBank::getRegClassForRegister(const Record *R) {
const CodeGenRegister *Reg = getReg(R);
const CodeGenRegisterClass *FoundRC = nullptr;
for (const auto &RC : getRegClasses()) {
@@ -2490,7 +2487,7 @@ const CodeGenRegisterClass *CodeGenRegBank::getRegClassForRegister(Record *R) {
}
const CodeGenRegisterClass *
-CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
+CodeGenRegBank::getMinimalPhysRegClass(const Record *RegRecord,
ValueTypeByHwMode *VT) {
const CodeGenRegister *Reg = getReg(RegRecord);
const CodeGenRegisterClass *BestRC = nullptr;
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index f0f53d346ab7ae..2fa6cab2afb892 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -63,7 +63,7 @@ struct MaskRolPair {
/// CodeGenSubRegIndex - Represents a sub-register index.
class CodeGenSubRegIndex {
- Record *const TheDef;
+ const Record *const TheDef;
std::string Name;
std::string Namespace;
@@ -85,7 +85,7 @@ class CodeGenSubRegIndex {
// indexes are not used to create new register classes.
bool Artificial;
- CodeGenSubRegIndex(Record *R, unsigned Enum, const CodeGenHwModes &CGH);
+ CodeGenSubRegIndex(const Record *R, unsigned Enum, const CodeGenHwModes &CGH);
CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
CodeGenSubRegIndex(CodeGenSubRegIndex &) = delete;
@@ -320,7 +320,7 @@ class CodeGenRegisterClass {
// List of super-classes, topologocally ordered to have the larger classes
// first. This is the same as sorting by EnumValue.
SmallVector<CodeGenRegisterClass *, 4> SuperClasses;
- Record *TheDef;
+ const Record *TheDef;
std::string Name;
// For a synthesized class, inherit missing properties from the nearest
@@ -368,7 +368,7 @@ class CodeGenRegisterClass {
// Return the Record that defined this class, or NULL if the class was
// created by TableGen.
- Record *getDef() const { return TheDef; }
+ const Record *getDef() const { return TheDef; }
std::string getNamespaceQualification() const;
const std::string &getName() const { return Name; }
@@ -473,7 +473,7 @@ class CodeGenRegisterClass {
void buildRegUnitSet(const CodeGenRegBank &RegBank,
std::vector<unsigned> &RegUnits) const;
- CodeGenRegisterClass(CodeGenRegBank &, Record *R);
+ CodeGenRegisterClass(CodeGenRegBank &, const Record *R);
CodeGenRegisterClass(CodeGenRegisterClass &) = delete;
// A key representing the parts of a register class used for forming
@@ -511,17 +511,17 @@ class CodeGenRegisterClass {
// register falls into (GPR, vector, fixed, etc.) without having to know
// specific information about the target architecture.
class CodeGenRegisterCategory {
- Record *TheDef;
+ const Record *TheDef;
std::string Name;
std::list<CodeGenRegisterClass *> Classes;
public:
- CodeGenRegisterCategory(CodeGenRegBank &, Record *R);
+ CodeGenRegisterCategory(CodeGenRegBank &, const Record *R);
CodeGenRegisterCategory(CodeGenRegisterCategory &) = delete;
// Return the Record that defined this class, or NULL if the class was
// created by TableGen.
- Record *getDef() const { return TheDef; }
+ const Record *getDef() const { return TheDef; }
std::string getName() const { return Name; }
std::list<CodeGenRegisterClass *> getClasses() const { return Classes; }
@@ -585,7 +585,7 @@ class CodeGenRegBank {
const CodeGenHwModes &CGH;
std::deque<CodeGenSubRegIndex> SubRegIndices;
- DenseMap<Record *, CodeGenSubRegIndex *> Def2SubRegIdx;
+ DenseMap<const Record *, CodeGenSubRegIndex *> Def2SubRegIdx;
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
@@ -612,7 +612,6 @@ class CodeGenRegBank {
// Register categories.
std::list<CodeGenRegisterCategory> RegCategories;
- DenseMap<Record *, CodeGenRegisterCategory *> Def2RCat;
using RCatKeyMap =
std::map<CodeGenRegisterClass::Key, CodeGenRegisterCategory *>;
RCatKeyMap Key2RCat;
@@ -677,7 +676,7 @@ class CodeGenRegBank {
void computeRegUnitLaneMasks();
public:
- CodeGenRegBank(RecordKeeper &, const CodeGenHwModes &);
+ CodeGenRegBank(const RecordKeeper &, const CodeGenHwModes &);
CodeGenRegBank(CodeGenRegBank &) = delete;
SetTheory &getSets() { return Sets; }
@@ -693,7 +692,7 @@ class CodeGenRegBank {
// Find a SubRegIndex from its Record def or add to the list if it does
// not exist there yet.
- CodeGenSubRegIndex *getSubRegIdx(Record *);
+ CodeGenSubRegIndex *getSubRegIdx(const Record *);
// Find a SubRegIndex from its Record def.
const CodeGenSubRegIndex *findSubRegIdx(const Record *Def) const;
@@ -785,14 +784,15 @@ class CodeGenRegBank {
/// class, return null. If the register is in multiple classes, and the
/// classes have a superset-subset relationship and the same set of types,
/// return the superclass. Otherwise return null.
- const CodeGenRegisterClass *getRegClassForRegister(Record *R);
+ const CodeGenRegisterClass *getRegClassForRegister(const Record *R);
// Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike
// getRegClassForRegister, this tries to find the smallest class containing
// the physical register. If \p VT is specified, it will only find classes
// with a matching type
const CodeGenRegisterClass *
- getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
+ getMinimalPhysRegClass(const Record *RegRecord,
+ ValueTypeByHwMode *VT = nullptr);
// Get the sum of unit weights.
unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
index 7425e7f48c2b03..e5e8225518b580 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
@@ -28,7 +28,8 @@ std::string llvm::getModeName(unsigned Mode) {
return (Twine('m') + Twine(Mode)).str();
}
-ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) {
+ValueTypeByHwMode::ValueTypeByHwMode(const Record *R,
+ const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))});
@@ -39,7 +40,8 @@ ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) {
PtrAddrSpace = R->getValueAsInt("AddrSpace");
}
-ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) {
+ValueTypeByHwMode::ValueTypeByHwMode(const Record *R, MVT T)
+ : ValueTypeByHwMode(T) {
if (R->isSubClassOf("PtrValueType"))
PtrAddrSpace = R->getValueAsInt("AddrSpace");
}
@@ -102,7 +104,7 @@ void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
LLVM_DUMP_METHOD
void ValueTypeByHwMode::dump() const { dbgs() << *this << '\n'; }
-ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec,
+ValueTypeByHwMode llvm::getValueTypeByHwMode(const Record *Rec,
const CodeGenHwModes &CGH) {
#ifndef NDEBUG
if (!Rec->isSubClassOf("ValueType"))
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h
index a6edf3c90da25b..4f11e8ecc7fcb9 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.h
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.h
@@ -152,8 +152,8 @@ template <typename InfoT> struct InfoByHwMode {
};
struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
- ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
- ValueTypeByHwMode(Record *R, MVT T);
+ ValueTypeByHwMode(const Record *R, const CodeGenHwModes &CGH);
+ ValueTypeByHwMode(const Record *R, MVT T);
ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); }
ValueTypeByHwMode() = default;
@@ -174,7 +174,8 @@ struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
}
};
-ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, const CodeGenHwModes &CGH);
+ValueTypeByHwMode getValueTypeByHwMode(const Record *Rec,
+ const CodeGenHwModes &CGH);
raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
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