[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

Alex Bradbury via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 11 03:24:34 PDT 2024

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https://github.com/asb approved this pull request.


https://github.com/llvm/llvm-project/pull/107446

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