[llvm] 7041163 - [AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 11 03:10:52 PDT 2024
Author: Simon Pilgrim
Date: 2024-09-11T11:06:55+01:00
New Revision: 704116373ae91a1b829dc3d3d269874fb27b579c
URL: https://github.com/llvm/llvm-project/commit/704116373ae91a1b829dc3d3d269874fb27b579c
DIFF: https://github.com/llvm/llvm-project/commit/704116373ae91a1b829dc3d3d269874fb27b579c.diff
LOG: [AMDGPU] Regenerate buffer intrinsic tests with update_llc_test_checks. NFC.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
index c27118446cc2f2..cafd903df2d564 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
@@ -1,47 +1,79 @@
-; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=UNPACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PACKED %s
-; GCN-LABEL: {{^}}buffer_load_format_d16_x:
-; GCN: buffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0
define amdgpu_ps half @buffer_load_format_d16_x(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_x:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: buffer_load_format_d16_x v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_x:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: buffer_load_format_d16_x v0, off, s[0:3], 0
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call half @llvm.amdgcn.raw.ptr.buffer.load.format.f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
ret half %data
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
-; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @buffer_load_format_d16_xy(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xy:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: buffer_load_format_d16_xy v[0:1], off, s[0:3], 0 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xy:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: buffer_load_format_d16_xy v0, off, s[0:3], 0
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.load.format.v2f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <2 x half> %data, i32 1
ret half %elt
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
-; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
define amdgpu_ps half @buffer_load_format_d16_xyz(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xyz:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: buffer_load_format_d16_xyz v[0:2], off, s[0:3], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xyz:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: buffer_load_format_d16_xyz v[0:1], off, s[0:3], 0
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_mov_b32_e32 v0, v1
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.raw.ptr.buffer.load.format.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <3 x half> %data, i32 2
ret half %elt
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
-; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyzw(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xyzw:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: buffer_load_format_d16_xyzw v[0:3], off, s[0:3], 0 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xyzw:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: buffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x half> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
%elt = extractelement <4 x half> %data, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
index 3a396b54f89ab7..39df6ec679e884 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
@@ -1,57 +1,107 @@
-; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=UNPACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PACKED %s
-; GCN-LABEL: {{^}}buffer_load_format_d16_x:
-; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_ps half @buffer_load_format_d16_x(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_x:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; UNPACKED-NEXT: buffer_load_format_d16_x v0, v0, s[0:3], 0 idxen ; encoding: [0x00,0x20,0x20,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_x:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PACKED-NEXT: buffer_load_format_d16_x v0, v0, s[0:3], 0 idxen
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call half @llvm.amdgcn.struct.ptr.buffer.load.format.f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
ret half %data
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xy:
-; UNPACKED: buffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @buffer_load_format_d16_xy(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xy:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; UNPACKED-NEXT: buffer_load_format_d16_xy v[0:1], v0, s[0:3], 0 idxen ; encoding: [0x00,0x20,0x24,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xy:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PACKED-NEXT: buffer_load_format_d16_xy v0, v0, s[0:3], 0 idxen
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v2f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <2 x half> %data, i32 1
ret half %elt
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xyz:
-; UNPACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyz(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xyz:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; UNPACKED-NEXT: buffer_load_format_d16_xyz v[0:2], v0, s[0:3], 0 idxen ; encoding: [0x00,0x20,0x28,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xyz:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PACKED-NEXT: buffer_load_format_d16_xyz v[0:1], v0, s[0:3], 0 idxen
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_mov_b32_e32 v0, v1
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <3 x half> %data, i32 2
ret half %elt
}
-; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw:
-; UNPACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PACKED: buffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @buffer_load_format_d16_xyzw(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_d16_xyzw:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; UNPACKED-NEXT: buffer_load_format_d16_xyzw v[0:3], v0, s[0:3], 0 idxen ; encoding: [0x00,0x20,0x2c,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_d16_xyzw:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PACKED-NEXT: buffer_load_format_d16_xyzw v[0:1], v0, s[0:3], 0 idxen
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
%elt = extractelement <4 x half> %data, i32 3
ret half %elt
}
-; GCN-LABEL: {{^}}buffer_load_format_i16_x:
-; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_ps half @buffer_load_format_i16_x(ptr addrspace(8) inreg %rsrc) {
+; UNPACKED-LABEL: buffer_load_format_i16_x:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; UNPACKED-NEXT: buffer_load_format_d16_x v0, v0, s[0:3], 0 idxen ; encoding: [0x00,0x20,0x20,0xe0,0x00,0x00,0x00,0x80]
+; UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; UNPACKED-NEXT: ; return to shader part epilog
+;
+; PACKED-LABEL: buffer_load_format_i16_x:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PACKED-NEXT: buffer_load_format_d16_x v0, v0, s[0:3], 0 idxen
+; PACKED-NEXT: s_waitcnt vmcnt(0)
+; PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call i16 @llvm.amdgcn.struct.ptr.buffer.load.format.i16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
%fdata = bitcast i16 %data to half
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
index 2f9e6b0a1cf526..55600cab8432b7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
@@ -1,12 +1,16 @@
-;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,SI
;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,VI
-;CHECK-LABEL: {{^}}buffer_load:
-;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
-;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(ptr addrspace(8) inreg) {
+; CHECK-LABEL: buffer_load:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v8, 0
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v8, s[0:3], 0 idxen
+; CHECK-NEXT: buffer_load_dwordx4 v[4:7], v8, s[0:3], 0 idxen glc
+; CHECK-NEXT: buffer_load_dwordx4 v[8:11], v8, s[0:3], 0 idxen slc
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
@@ -17,106 +21,165 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs:
-;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs(ptr addrspace(8) inreg) {
+; CHECK-LABEL: buffer_load_immoffs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen offset:40
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 40, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
-;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc
-;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:4
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs_large(ptr addrspace(8) inreg) {
+; CHECK-LABEL: buffer_load_immoffs_large:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_movk_i32 s4, 0x1ffc
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], s4 idxen offset:4
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 4, i32 8188, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_idx:
-;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_idx(ptr addrspace(8) inreg, i32) {
+; CHECK-LABEL: buffer_load_idx:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 %1, i32 0, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs:
-;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs(ptr addrspace(8) inreg, i32) {
+; CHECK-LABEL: buffer_load_ofs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 %1, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
-;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs_imm(ptr addrspace(8) inreg, i32) {
+; CHECK-LABEL: buffer_load_ofs_imm:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, v0
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%ofs = add i32 %1, 60
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 %ofs, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_both:
-;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_both(ptr addrspace(8) inreg, i32, i32) {
+; CHECK-LABEL: buffer_load_both:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 %1, i32 %2, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_both_reversed:
-;CHECK: v_mov_b32_e32 v2, v0
-;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_both_reversed(ptr addrspace(8) inreg, i32, i32) {
+; CHECK-LABEL: buffer_load_both_reversed:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v2, v0
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 %2, i32 %1, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_x1:
-;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps float @buffer_load_x1(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: buffer_load_x1:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
ret float %data
}
-;CHECK-LABEL: {{^}}buffer_load_x2:
-;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <2 x float> @buffer_load_x2(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: buffer_load_x2:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x float> @llvm.amdgcn.struct.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
ret <2 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_negative_offset:
-;CHECK: v_add_{{[iu]}}32_e32 {{v[0-9]+}}, vcc, -16, v0
-;CHECK: buffer_load_dwordx4 v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen
define amdgpu_ps <4 x float> @buffer_load_negative_offset(ptr addrspace(8) inreg, i32 %ofs) {
+; SI-LABEL: buffer_load_negative_offset:
+; SI: ; %bb.0: ; %main_body
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: v_add_i32_e32 v1, vcc, -16, v0
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: buffer_load_negative_offset:
+; VI: ; %bb.0: ; %main_body
+; VI-NEXT: s_mov_b32 s4, 0
+; VI-NEXT: v_add_u32_e32 v1, vcc, -16, v0
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: ; return to shader part epilog
main_body:
%ofs.1 = add i32 %ofs, -16
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 %ofs.1, i32 0, i32 0)
ret <4 x float> %data
}
-; SI won't merge ds memory operations, because of the signed offset bug, so
-; we only have check lines for VI.
-; CHECK-LABEL: buffer_load_mmo:
-; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
-; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
+; SI won't merge ds memory operations, because of the signed offset bug.
define amdgpu_ps float @buffer_load_mmo(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %lds) {
+; SI-LABEL: buffer_load_mmo:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: v_mov_b32_e32 v2, 0
+; SI-NEXT: buffer_load_dword v1, v2, s[0:3], 0 idxen
+; SI-NEXT: s_mov_b32 m0, -1
+; SI-NEXT: ds_write_b32 v0, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 16, v0
+; SI-NEXT: ds_write_b32 v0, v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, v1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: buffer_load_mmo:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: v_mov_b32_e32 v2, 0
+; VI-NEXT: buffer_load_dword v1, v2, s[0:3], 0 idxen
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_write2_b32 v0, v2, v2 offset1:4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, v1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ; return to shader part epilog
entry:
store float 0.0, ptr addrspace(3) %lds
%val = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
@@ -125,12 +188,15 @@ entry:
ret float %val
}
-;CHECK-LABEL: {{^}}buffer_load_int:
-;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_load_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_load_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc
-;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(ptr addrspace(8) inreg) {
+; CHECK-LABEL: buffer_load_int:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v6, 0
+; CHECK-NEXT: buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 idxen
+; CHECK-NEXT: buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 idxen glc
+; CHECK-NEXT: buffer_load_dword v6, v6, s[0:3], 0 idxen slc
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x i32> @llvm.amdgcn.struct.ptr.buffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <2 x i32> @llvm.amdgcn.struct.ptr.buffer.load.v2i32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
@@ -144,13 +210,13 @@ main_body:
ret {<4 x float>, <2 x float>, float} %r2
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_ubyte:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @struct_ptr_buffer_load_ubyte(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: struct_ptr_buffer_load_ubyte:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%tmp = call i8 @llvm.amdgcn.struct.ptr.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
%tmp2 = zext i8 %tmp to i32
@@ -158,13 +224,13 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_ushort:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
-;CHECK-NEXT: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @struct_ptr_buffer_load_ushort(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: struct_ptr_buffer_load_ushort:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%tmp = call i16 @llvm.amdgcn.struct.ptr.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
%tmp2 = zext i16 %tmp to i32
@@ -172,13 +238,13 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_sbyte:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
-;CHECK-NEXT: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @struct_ptr_buffer_load_sbyte(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: struct_ptr_buffer_load_sbyte:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_sbyte v0, v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%tmp = call i8 @llvm.amdgcn.struct.ptr.buffer.load.i8(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
%tmp2 = sext i8 %tmp to i32
@@ -186,13 +252,13 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_sshort:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
-;CHECK-NEXT: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @struct_ptr_buffer_load_sshort(ptr addrspace(8) inreg %rsrc, i32 %idx, i32 %ofs) {
+; CHECK-LABEL: struct_ptr_buffer_load_sshort:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_sshort v0, v[0:1], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
+; CHECK-NEXT: ; return to shader part epilog
main_body:
%tmp = call i16 @llvm.amdgcn.struct.ptr.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
%tmp2 = sext i16 %tmp to i32
@@ -200,72 +266,84 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b16 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_f16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_f16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_ushort v1, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b16 v0, v1
+; CHECK-NEXT: s_endpgm
main_body:
%val = call half @llvm.amdgcn.struct.ptr.buffer.load.f16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store half %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_v2f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b32 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_v2f16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_v2f16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dword v1, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b32 v0, v1
+; CHECK-NEXT: s_endpgm
main_body:
%val = call <2 x half> @llvm.amdgcn.struct.ptr.buffer.load.v2f16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store <2 x half> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_v4f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b64 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_v4f16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_v4f16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dwordx2 v[1:2], v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b64 v0, v[1:2]
+; CHECK-NEXT: s_endpgm
main_body:
%val = call <4 x half> @llvm.amdgcn.struct.ptr.buffer.load.v4f16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store <4 x half> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b16 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_i16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_i16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_ushort v1, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b16 v0, v1
+; CHECK-NEXT: s_endpgm
main_body:
%val = call i16 @llvm.amdgcn.struct.ptr.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store i16 %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_v2i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b32 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_v2i16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_v2i16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dword v1, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b32 v0, v1
+; CHECK-NEXT: s_endpgm
main_body:
%val = call <2 x i16> @llvm.amdgcn.struct.ptr.buffer.load.v2i16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store <2 x i16> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_load_v4i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_write_b64 v0, [[VAL]]
define amdgpu_ps void @struct_ptr_buffer_load_v4i16(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %ptr, i32 %idx) {
+; CHECK-LABEL: struct_ptr_buffer_load_v4i16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_load_dwordx2 v[1:2], v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: ds_write_b64 v0, v[1:2]
+; CHECK-NEXT: s_endpgm
main_body:
%val = call <4 x i16> @llvm.amdgcn.struct.ptr.buffer.load.v4i16(ptr addrspace(8) %rsrc, i32 %idx, i32 0, i32 0, i32 0)
store <4 x i16> %val, ptr addrspace(3) %ptr
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
index 8109fca4a043ab..58b422dd6a7510 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
@@ -1,85 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED %s
-; GCN-LABEL: {{^}}buffer_store_format_d16_x:
-; GCN: s_load_dword s[[LO:[0-9]+]]
-; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
-; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_x(ptr addrspace(8) %rsrc, [8 x i32], half %data, [8 x i32], i32 %index) {
+; GCN-LABEL: buffer_store_format_d16_x:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_load_dword s4, s[6:7], 0x30
+; GCN-NEXT: s_load_dword s5, s[6:7], 0x54
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 idxen
+; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.f16(half %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_format_d16_xy:
-
-; UNPACKED: s_load_dwordx2 s[[[S_DATA:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], s[[S_DATA]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], s[[S_DATA]], 0xffff{{$}}
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
-; UNPACKED: buffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-
-; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xy(ptr addrspace(8) %rsrc, <2 x half> %data, i32 %index) {
+; UNPACKED-LABEL: buffer_store_format_d16_xy:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; UNPACKED-NEXT: s_lshr_b32 s6, s4, 16
+; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; UNPACKED-NEXT: v_mov_b32_e32 v1, s6
+; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; UNPACKED-NEXT: buffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 idxen
+; UNPACKED-NEXT: s_endpgm
+;
+; PACKED-LABEL: buffer_store_format_d16_xy:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; PACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PACKED-NEXT: v_mov_b32_e32 v0, s4
+; PACKED-NEXT: v_mov_b32_e32 v1, s5
+; PACKED-NEXT: buffer_store_format_d16_xy v0, v1, s[0:3], 0 idxen
+; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f16(<2 x half> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_format_d16_xyz:
-; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
-
-; UNPACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-
-; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
-
-; PACKED: buffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyz(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %index) {
+; UNPACKED-LABEL: buffer_store_format_d16_xyz:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; UNPACKED-NEXT: s_load_dword s6, s[6:7], 0x18
+; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; UNPACKED-NEXT: s_lshr_b32 s7, s4, 16
+; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; UNPACKED-NEXT: v_mov_b32_e32 v1, s7
+; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; UNPACKED-NEXT: v_mov_b32_e32 v3, s6
+; UNPACKED-NEXT: buffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 idxen
+; UNPACKED-NEXT: s_endpgm
+;
+; PACKED-LABEL: buffer_store_format_d16_xyz:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; PACKED-NEXT: s_load_dword s8, s[6:7], 0x18
+; PACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; PACKED-NEXT: v_mov_b32_e32 v0, s4
+; PACKED-NEXT: v_mov_b32_e32 v1, s5
+; PACKED-NEXT: v_mov_b32_e32 v2, s8
+; PACKED-NEXT: buffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 idxen
+; PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v3f16(<3 x half> %data_subvec, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_format_d16_xyzw:
-; GCN-DAG: s_load_dwordx2 s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
-
-; UNPACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
-
-; PACKED: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
-
-; PACKED: buffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_d16_xyzw(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %index) {
+; UNPACKED-LABEL: buffer_store_format_d16_xyzw:
+; UNPACKED: ; %bb.0: ; %main_body
+; UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; UNPACKED-NEXT: s_load_dword s6, s[6:7], 0x18
+; UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; UNPACKED-NEXT: s_lshr_b32 s7, s5, 16
+; UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; UNPACKED-NEXT: s_lshr_b32 s8, s4, 16
+; UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; UNPACKED-NEXT: v_mov_b32_e32 v1, s8
+; UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; UNPACKED-NEXT: v_mov_b32_e32 v3, s7
+; UNPACKED-NEXT: v_mov_b32_e32 v4, s6
+; UNPACKED-NEXT: buffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 idxen
+; UNPACKED-NEXT: s_endpgm
+;
+; PACKED-LABEL: buffer_store_format_d16_xyzw:
+; PACKED: ; %bb.0: ; %main_body
+; PACKED-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x10
+; PACKED-NEXT: s_load_dword s8, s[6:7], 0x18
+; PACKED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PACKED-NEXT: v_mov_b32_e32 v0, s4
+; PACKED-NEXT: v_mov_b32_e32 v1, s5
+; PACKED-NEXT: v_mov_b32_e32 v2, s8
+; PACKED-NEXT: buffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 idxen
+; PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f16(<4 x half> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_format_i16_x:
-; GCN: s_load_dword s[[LO:[0-9]+]]
-; GCN: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[LO]]
-; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
define amdgpu_kernel void @buffer_store_format_i16_x(ptr addrspace(8) %rsrc, [8 x i32], i16 %data, [8 x i32], i32 %index) {
+; GCN-LABEL: buffer_store_format_i16_x:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_load_dword s4, s[6:7], 0x30
+; GCN-NEXT: s_load_dword s5, s[6:7], 0x54
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: buffer_store_format_d16_x v0, v1, s[0:3], 0 idxen
+; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.i16(i16 %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
index 13217b24dcd4b4..61a08d96986b09 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
@@ -1,12 +1,15 @@
-;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
-;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=CHECK,SI %s
+;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VI %s
-;CHECK-LABEL: {{^}}buffer_store:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_store_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_store_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
define amdgpu_ps void @buffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {
+; CHECK-LABEL: buffer_store:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v12, 0
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v12, s[0:3], 0 idxen
+; CHECK-NEXT: buffer_store_format_xyzw v[4:7], v12, s[0:3], 0 idxen glc
+; CHECK-NEXT: buffer_store_format_xyzw v[8:11], v12, s[0:3], 0 idxen slc
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
@@ -14,47 +17,56 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_immoffs:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
define amdgpu_ps void @buffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {
+; CHECK-LABEL: buffer_store_immoffs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v4, 0
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen offset:42
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_idx:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float>, i32) {
+; CHECK-LABEL: buffer_store_idx:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_ofs:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float>, i32) {
+; CHECK-LABEL: buffer_store_ofs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: v_mov_b32_e32 v5, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 %2, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_both:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
+; CHECK-LABEL: buffer_store_both:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 %3, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_both_reversed:
-;CHECK: v_mov_b32_e32 v6, v4
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_both_reversed(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
+; CHECK-LABEL: buffer_store_both_reversed:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v6, v4
+; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %3, i32 %2, i32 0, i32 0)
ret void
@@ -62,14 +74,23 @@ main_body:
; Ideally, the register allocator would avoid the wait here
;
-;CHECK-LABEL: {{^}}buffer_store_wait:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
-;VERDE: s_waitcnt expcnt(0)
-;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float>, i32, i32, i32) {
+; SI-LABEL: buffer_store_wait:
+; SI: ; %bb.0: ; %main_body
+; SI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: buffer_store_wait:
+; VI: ; %bb.0: ; %main_body
+; VI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
+; VI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 %3, i32 0, i32 0, i32 0)
@@ -77,28 +98,31 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_x1:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %index) {
+; CHECK-LABEL: buffer_store_x1:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.f32(float %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_x1_i32:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_x1_i32(ptr addrspace(8) inreg %rsrc, i32 %data, i32 %index) {
+; CHECK-LABEL: buffer_store_x1_i32:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.i32(i32 %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_x2:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %index) {
+; CHECK-LABEL: buffer_store_x2:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f32(<2 x float> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
index e52af313607640..d08623f685e855 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
@@ -1,12 +1,15 @@
-;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
-;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-;CHECK-LABEL: {{^}}buffer_store:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_store_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_store_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=CHECK,SI %s
+;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VI %s
+
define amdgpu_ps void @buffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {
+; CHECK-LABEL: buffer_store:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v12, 0
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v12, s[0:3], 0 idxen
+; CHECK-NEXT: buffer_store_dwordx4 v[4:7], v12, s[0:3], 0 idxen glc
+; CHECK-NEXT: buffer_store_dwordx4 v[8:11], v12, s[0:3], 0 idxen slc
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
@@ -14,62 +17,79 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_immoffs:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
define amdgpu_ps void @buffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {
+; CHECK-LABEL: buffer_store_immoffs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v4, 0
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen offset:42
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_idx:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float>, i32) {
+; CHECK-LABEL: buffer_store_idx:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_ofs:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float>, i32) {
+; CHECK-LABEL: buffer_store_ofs:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: v_mov_b32_e32 v5, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 %2, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_both:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
+; CHECK-LABEL: buffer_store_both:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 %3, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_both_reversed:
-;CHECK: v_mov_b32_e32 v6, v4
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
define amdgpu_ps void @buffer_store_both_reversed(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
+; CHECK-LABEL: buffer_store_both_reversed:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v6, v4
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %3, i32 %2, i32 0, i32 0)
ret void
}
; Ideally, the register allocator would avoid the wait here
-;
-;CHECK-LABEL: {{^}}buffer_store_wait:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
-;VERDE: s_waitcnt expcnt(0)
-;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float>, i32, i32, i32) {
+; SI-LABEL: buffer_store_wait:
+; SI: ; %bb.0: ; %main_body
+; SI-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: buffer_store_wait:
+; VI: ; %bb.0: ; %main_body
+; VI-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
+; VI-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 %3, i32 0, i32 0, i32 0)
@@ -77,30 +97,34 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_x1:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %index) {
+; CHECK-LABEL: buffer_store_x1:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.f32(float %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_x2:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %index) #0 {
+; CHECK-LABEL: buffer_store_x2:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v2f32(<2 x float> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}buffer_store_int:
-;CHECK-NOT: s_waitcnt
-;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_store_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_store_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc
define amdgpu_ps void @buffer_store_int(ptr addrspace(8) inreg, <4 x i32>, <2 x i32>, i32) {
+; CHECK-LABEL: buffer_store_int:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_mov_b32_e32 v7, 0
+; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v7, s[0:3], 0 idxen
+; CHECK-NEXT: buffer_store_dwordx2 v[4:5], v7, s[0:3], 0 idxen glc
+; CHECK-NEXT: buffer_store_dword v6, v7, s[0:3], 0 idxen slc
+; CHECK-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.store.v4i32(<4 x i32> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.struct.ptr.buffer.store.v2i32(<2 x i32> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
@@ -108,12 +132,12 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_byte:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
-;CHECK-NEXT: buffer_store_byte v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen
-;CHECK-NEXT: s_endpgm
define amdgpu_ps void @struct_ptr_buffer_store_byte(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {
+; CHECK-LABEL: struct_ptr_buffer_store_byte:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: buffer_store_byte v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
%v2 = fptoui float %v1 to i32
%v3 = trunc i32 %v2 to i8
@@ -121,39 +145,63 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: v_cvt_f16_f32_e32 v{{[0-9]}}, v{{[0-9]}}
-;CHECK-NEXT: buffer_store_short v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen
-;CHECK-NEXT: s_endpgm
define amdgpu_ps void @struct_ptr_buffer_store_f16(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {
+; CHECK-LABEL: struct_ptr_buffer_store_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CHECK-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
%v2 = fptrunc float %v1 to half
call void @llvm.amdgcn.struct.ptr.buffer.store.f16(half %v2, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_v2f16:
-;CHECK-NEXT: %bb.
-;CHECK: buffer_store_dword v0, {{v[0-9]+}}, s[0:3], 0 idxen
define amdgpu_ps void @struct_ptr_buffer_store_v2f16(ptr addrspace(8) inreg %rsrc, <2 x half> %v1, i32 %index) {
+; SI-LABEL: struct_ptr_buffer_store_v2f16:
+; SI: ; %bb.0:
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: struct_ptr_buffer_store_v2f16:
+; VI: ; %bb.0:
+; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
call void @llvm.amdgcn.struct.ptr.buffer.store.v2f16(<2 x half> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_v4f16:
-;CHECK-NEXT: %bb.
-;CHECK: buffer_store_dwordx2 v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen
define amdgpu_ps void @struct_ptr_buffer_store_v4f16(ptr addrspace(8) inreg %rsrc, <4 x half> %v1, i32 %index) {
+; SI-LABEL: struct_ptr_buffer_store_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: buffer_store_dwordx2 v[0:1], v4, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: struct_ptr_buffer_store_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
call void @llvm.amdgcn.struct.ptr.buffer.store.v4f16(<4 x half> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
-;CHECK-NEXT: buffer_store_short v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen
-;CHECK-NEXT: s_endpgm
define amdgpu_ps void @struct_ptr_buffer_store_i16(ptr addrspace(8) inreg %rsrc, float %v1, i32 %index) {
+; CHECK-LABEL: struct_ptr_buffer_store_i16:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen
+; CHECK-NEXT: s_endpgm
main_body:
%v2 = fptoui float %v1 to i32
%v3 = trunc i32 %v2 to i16
@@ -161,18 +209,39 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_vif16:
-;CHECK-NEXT: %bb.
-;CHECK: buffer_store_dword v0, {{v[0-9]+}}, s[0:3], 0 idxen
define amdgpu_ps void @struct_ptr_buffer_store_vif16(ptr addrspace(8) inreg %rsrc, <2 x i16> %v1, i32 %index) {
+; SI-LABEL: struct_ptr_buffer_store_vif16:
+; SI: ; %bb.0:
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: struct_ptr_buffer_store_vif16:
+; VI: ; %bb.0:
+; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
call void @llvm.amdgcn.struct.ptr.buffer.store.v2i16(<2 x i16> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
-;CHECK-LABEL: {{^}}struct_ptr_buffer_store_v4i16:
-;CHECK-NEXT: %bb.
-;CHECK: buffer_store_dwordx2 v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen
define amdgpu_ps void @struct_ptr_buffer_store_v4i16(ptr addrspace(8) inreg %rsrc, <4 x i16> %v1, i32 %index) {
+; SI-LABEL: struct_ptr_buffer_store_v4i16:
+; SI: ; %bb.0:
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_or_b32_e32 v1, v0, v1
+; SI-NEXT: buffer_store_dwordx2 v[1:2], v4, s[0:3], 0 idxen
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: struct_ptr_buffer_store_v4i16:
+; VI: ; %bb.0:
+; VI-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
+; VI-NEXT: s_endpgm
call void @llvm.amdgcn.struct.ptr.buffer.store.v4i16(<4 x i16> %v1, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
ret void
}
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