[llvm] [AMDGPU][MC] Implement fft and rotate modes for ds_swizzle_b32 (PR #108064)

[Jun Wang via llvm-commits]

================
@@ -8141,6 +8143,56 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
   return true;
 }
 
+bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
+  using namespace llvm::AMDGPU::Swizzle;
+
+  if (!skipToken(AsmToken::Comma, "expected a comma"))
+    return false;
+
+  SMLoc Loc = getLoc();
+
+  int64_t Type;
+
+  if (!parseExpr(Type))
+    return false;
+
+  if (Type != FFT_NO_SWIZZLE && Type != FFT_SWIZZLE_00 &&
+      Type != FFT_SWIZZLE_10) {
+    const std::string ErrMsg = "invalid FFT swizzle type: must be " +
+                               std::to_string(FFT_SWIZZLE_00) + ", " +
+                               std::to_string(FFT_SWIZZLE_10) + ", or " +
+                               std::to_string(FFT_NO_SWIZZLE);
----------------
jwanggit86 wrote:

Good point. It's possible the ISA doc lists 0x00, 0x10, and 0x1f as examples, not enumeration of allowed values. Will fix.

https://github.com/llvm/llvm-project/pull/108064