[llvm] [RISC-V][GISEL] Select G_BITCAST for scalable vectors (PR #101486)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Jiahan Xie (jiahanxie353)

<details>
<summary>Changes</summary>

Just got started to work on instruction selection after landing [the regbankselect pass for scalable vector loads/stores](https://github.com/llvm/llvm-project/pull/99932).

Seems like [`selectImpl`](https://github.com/llvm/llvm-project/blob/e1451236a0a07f1ee4ba5fe3ae2464a82a37c25c/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp#L553) can capture loads/stores, but is not able to work for [`G_BITCAST`](https://github.com/llvm/llvm-project/blob/e1451236a0a07f1ee4ba5fe3ae2464a82a37c25c/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir#L1007) out of the box.

Would a bitcast essentially being the same semantics as a `copy`? I was also looking at [how AArch64 did it](https://github.com/llvm/llvm-project/blob/e1451236a0a07f1ee4ba5fe3ae2464a82a37c25c/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir#L37), seems like they are also just doing a copy? I'm not entirely sure.

Can I get some pointers? @<!-- -->topperc @<!-- -->michaelmaitland  Thanks! 

---
Full diff: https://github.com/llvm/llvm-project/pull/101486.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index fdb1ebace00107..2243a22a167cab 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -559,6 +559,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_TRUNC:
   case TargetOpcode::G_FREEZE:
+  case TargetOpcode::G_BITCAST:
     return selectCopy(MI, MRI);
   case TargetOpcode::G_CONSTANT: {
     Register DstReg = MI.getOperand(0).getReg();

``````````

</details>


https://github.com/llvm/llvm-project/pull/101486