[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

[Alex Bradbury via llvm-commits]

https://github.com/asb approved this pull request.

LGTM in that the reasoning makes sense to me and I can't see problems from going through the code. That said, it's been a while since I added a new register class.

I think it would be nice to have a brief comment in RISCVRegisterInfo.td explaining why we're defining this register class and how it's used. Perhaps that makes more sense once you make similar changes for zfinx, but in general I find such in-tree documentation of intent really helpful.

You say that fsgnj gives better results vs mv - I'm assuming this is for real world code? Because for the modified in-tree tests, surely using `mv` where possible is better due to being potentially compressible? Happy to go with your judgement, but it probably deserves a TODO/FIXME somewhere like the tests to note that a semantically equivalent mv would be more compressible (and so someone sufficiently motivated might later pick it up).

https://github.com/llvm/llvm-project/pull/107446