[llvm] 1581183 - Revert "[llvm-ml] Fix RIP-relative addressing for ptr operands (#107618)"

Martin Storsjö via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 10 00:58:14 PDT 2024


Author: Martin Storsjö
Date: 2024-09-10T10:35:09+03:00
New Revision: 1581183d59b87760521e7223df3ff25c57e72fb3

URL: https://github.com/llvm/llvm-project/commit/1581183d59b87760521e7223df3ff25c57e72fb3
DIFF: https://github.com/llvm/llvm-project/commit/1581183d59b87760521e7223df3ff25c57e72fb3.diff

LOG: Revert "[llvm-ml] Fix RIP-relative addressing for ptr operands (#107618)"

This reverts commit 7543d09b852695187d08aa5d56d50016fea8f706.

This change caused failed asserts when building the openmp assembly
sources, reproducible with:

    $ llvm-ml -m64 -D_M_AMD64 -c -Fo out.obj openmp/runtime/src/z_Windows_NT-586_asm.asm
    llvm-ml: ../lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:624: void {anonymous}::X86MCCodeEmitter::emitMemModRMByte(const llvm::MCInst&, unsigned int, unsigned int, uint64_t, {anonymous}::PrefixKind, uint64_t, llvm::SmallVectorImpl<char>&, llvm::SmallVectorImpl<llvm::MCFixup>&, const llvm::MCSubtargetInfo&, bool) const: Assertion `IndexReg.getReg() == 0 && !ForceSIB && "Invalid rip-relative address"' failed.

The assert can also be triggered with one lone instruction:

    lea rdx, QWORD PTR [rax*8+16]

Added: 
    

Modified: 
    llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/test/tools/llvm-ml/rip_relative_addressing.asm

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index e88dc9cfbf4877..03f49306c2b7b5 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2707,7 +2707,7 @@ bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
   bool MaybeDirectBranchDest = true;
 
   if (Parser.isParsingMasm()) {
-    if (is64BitMode() && (PtrInOperand || SM.getElementSize() > 0)) {
+    if (is64BitMode() && SM.getElementSize() > 0) {
       DefaultBaseReg = X86::RIP;
     }
     if (IsUnconditionalBranch) {

diff  --git a/llvm/test/tools/llvm-ml/rip_relative_addressing.asm b/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
index cdd984ee6a8522..d237e84435b7d6 100644
--- a/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
+++ b/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
@@ -53,10 +53,4 @@ mov eax, [t8]
 ; CHECK-LABEL: t8:
 ; CHECK: mov eax, dword ptr [t8]
 
-t9:
-mov eax, dword ptr [bar]
-; CHECK-LABEL: t9:
-; CHECK-32: mov eax, dword ptr [bar]
-; CHECK-64: mov eax, dword ptr [rip + bar]
-
-END
+END
\ No newline at end of file


        


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