[llvm] b71d88c - [RISCV] Constrain passthru regclass in vmerge -> vmv peephole

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2024-09-10T13:26:07+08:00
New Revision: b71d88ca5bf42533b822be782ed9066e68011e95

URL: https://github.com/llvm/llvm-project/commit/b71d88ca5bf42533b822be782ed9066e68011e95
DIFF: https://github.com/llvm/llvm-project/commit/b71d88ca5bf42533b822be782ed9066e68011e95.diff

LOG: [RISCV] Constrain passthru regclass in vmerge -> vmv peephole

In #107827 we now set true's passthru to the false operand if it was
undef. We need to remember to also constrain the regclass in case true
is a masked pseudo which needs its passthrus to be in VR[M*]NoV0

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 1bad53f807546c..384eb9d7b94642 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -421,6 +421,10 @@ bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
         !ensureDominates(MI.getOperand(2), *True))
       return false;
     True->getOperand(1).setReg(MI.getOperand(2).getReg());
+    // If True is masked then its passthru needs to be in VRNoV0.
+    MRI->constrainRegClass(True->getOperand(1).getReg(),
+                           TII->getRegClass(True->getDesc(), 1, TRI,
+                                            *True->getParent()->getParent()));
   }
 
   MI.setDesc(TII->get(NewOpc));

diff  --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
index 2383842bc49d97..e2f1fe4094b5c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -152,7 +152,7 @@ body: |
     ; CHECK-NEXT: $v0 = COPY %mask
     ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, $v0, 4, 5 /* e32 */, 1 /* ta, mu */
     ; CHECK-NEXT: $v0 = COPY %mask
-    %false:vrnov0 = COPY $v8
+    %false:vr = COPY $v8
     %mask:vr = COPY $v0
     $v0 = COPY %mask
     %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, $v0, 4, 5 /* e32 */, 0 /* tu, mu */