[llvm] 7543d09 - [llvm-ml] Fix RIP-relative addressing for ptr operands (#107618)

[via llvm-commits]

Author: Andrew Ng
Date: 2024-09-09T13:18:41-04:00
New Revision: 7543d09b852695187d08aa5d56d50016fea8f706

URL: https://github.com/llvm/llvm-project/commit/7543d09b852695187d08aa5d56d50016fea8f706
DIFF: https://github.com/llvm/llvm-project/commit/7543d09b852695187d08aa5d56d50016fea8f706.diff

LOG: [llvm-ml] Fix RIP-relative addressing for ptr operands (#107618)

Fixes #54773

Added: 
    

Modified: 
    llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/test/tools/llvm-ml/rip_relative_addressing.asm

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 03f49306c2b7b5..e88dc9cfbf4877 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2707,7 +2707,7 @@ bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
   bool MaybeDirectBranchDest = true;
 
   if (Parser.isParsingMasm()) {
-    if (is64BitMode() && SM.getElementSize() > 0) {
+    if (is64BitMode() && (PtrInOperand || SM.getElementSize() > 0)) {
       DefaultBaseReg = X86::RIP;
     }
     if (IsUnconditionalBranch) {

diff  --git a/llvm/test/tools/llvm-ml/rip_relative_addressing.asm b/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
index d237e84435b7d6..cdd984ee6a8522 100644
--- a/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
+++ b/llvm/test/tools/llvm-ml/rip_relative_addressing.asm
@@ -53,4 +53,10 @@ mov eax, [t8]
 ; CHECK-LABEL: t8:
 ; CHECK: mov eax, dword ptr [t8]
 
-END
\ No newline at end of file
+t9:
+mov eax, dword ptr [bar]
+; CHECK-LABEL: t9:
+; CHECK-32: mov eax, dword ptr [bar]
+; CHECK-64: mov eax, dword ptr [rip + bar]
+
+END