[llvm] [AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (PR #107889)

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git-clang-format --diff 111932d5cae0199d9c59669b37232a011f8b8757 03605287cb6ae1f7bb4da00afc5c180d184ebf52 --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 208af0634f..8064c07310 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1072,7 +1072,8 @@ void SIWholeQuadMode::lowerBlock(MachineBasicBlock &MBB) {
     case AMDGPU::V_SET_INACTIVE_B32:
       if (ActiveLanesReg) {
         LiveInterval &LI = LIS->getInterval(MI.getOperand(5).getReg());
-        MRI->constrainRegClass(ActiveLanesReg, TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
+        MRI->constrainRegClass(
+            ActiveLanesReg, TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
         MI.getOperand(5).setReg(ActiveLanesReg);
         LIS->shrinkToUses(&LI);
       } else {

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https://github.com/llvm/llvm-project/pull/107889