[llvm] [loongarch][DAG][FREEZE] Fix crash when FREEZE a half(f16) type on loongarch (PR #107791)

YANG Xudong via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 8 17:49:14 PDT 2024


https://github.com/yxd-ym created https://github.com/llvm/llvm-project/pull/107791

For zig with LLVM 19.1.0rc4, we are seeing the following error when bootstrapping a `loongarch64-linux-musl` target.

https://github.com/ziglang/zig-bootstrap/issues/164#issuecomment-2332357069

It seems that this issue is caused by `PromoteFloatResult` is not handling FREEZE OP on loongarch.

Here is the reproduction of the error: https://godbolt.org/z/PPfvWjjG5

This patch adds the FREEZE OP handling with `PromoteFloatRes_UnaryOp` and adds a test case.


See: loongarch's handling of `half`:
- https://github.com/llvm/llvm-project/issues/93894
- https://github.com/llvm/llvm-project/pull/94456

Also see: other float promotion FREEZE handling
- https://github.com/llvm/llvm-project/commit/0019c2f194a5e1f4cd65c5284e204328cc40ab3d

>From d258ec376ddf4855c95a37d18f0969d4e1435ea1 Mon Sep 17 00:00:00 2001
From: YANG Xudong <yangxudong at ymatrix.cn>
Date: Sun, 8 Sep 2024 17:47:18 +0800
Subject: [PATCH 1/2] handle FREEZE in PromoteFloatResult

---
 llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index b5c80005a0ecc1..51357dad5b30ec 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -2655,6 +2655,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
     case ISD::FLOG10:
     case ISD::FNEARBYINT:
     case ISD::FNEG:
+    case ISD::FREEZE:
     case ISD::FRINT:
     case ISD::FROUND:
     case ISD::FROUNDEVEN:

>From e4b50bc35fe43a1e443ab65408872dbe5b3d7b0b Mon Sep 17 00:00:00 2001
From: YANG Xudong <yangxudong at ymatrix.cn>
Date: Sun, 8 Sep 2024 17:47:54 +0800
Subject: [PATCH 2/2] add fp16-promote test for loongarch

---
 llvm/test/CodeGen/LoongArch/fp16-promote.ll | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/test/CodeGen/LoongArch/fp16-promote.ll b/llvm/test/CodeGen/LoongArch/fp16-promote.ll
index 75f920b43a06ce..a139428f2d61e9 100644
--- a/llvm/test/CodeGen/LoongArch/fp16-promote.ll
+++ b/llvm/test/CodeGen/LoongArch/fp16-promote.ll
@@ -324,3 +324,18 @@ define void @test_fmul_mem(ptr %p, ptr %q) nounwind {
   store half %r, ptr %p
   ret void
 }
+
+define half @freeze_half() nounwind {
+; LA32-LABEL: freeze_half:
+; LA32:       # %bb.0:
+; LA32-NEXT:    fadd.s	$fa0, $fa0, $fa0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: freeze_half:
+; LA64:       # %bb.0:
+; LA64-NEXT:    fadd.s	$fa0, $fa0, $fa0
+; LA64-NEXT:    ret
+  %y1 = freeze half undef
+  %t1 = fadd half %y1, %y1
+  ret half %t1
+}



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