[llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #107760)

[Kazu Hirata via llvm-commits]

https://github.com/kazutakahirata updated https://github.com/llvm/llvm-project/pull/107760

>From 3a2515204302bfaa96ae934a06c247e6bd92ffd4 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 8 Sep 2024 07:37:59 -0700
Subject: [PATCH 1/2] [Hexagon] Avoid repeated hash lookups (NFC)

---
 llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 6 ++----
 llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp     | 6 +-----
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 88b4defc754ab1..f5f25523ca9d54 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -297,10 +297,8 @@ LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
       unsigned Exec) {
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  ReferenceMap::iterator F = Map.find(RR.Reg);
-  if (F == Map.end())
-    Map.insert(std::make_pair(RR.Reg, Mask));
-  else
+  auto [F, Inserted] = Map.try_emplace(RR.Reg, Mask);
+  if (!Inserted)
     F->second |= Mask;
 }
 
diff --git a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
index fe0875a3d6a4f3..e042522663867a 100644
--- a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
@@ -92,11 +92,7 @@ bool HexagonTfrCleanup::isIntReg(unsigned Reg, bool &Is32) {
 // Assign given value V32 to the specified the register R32 in the map. Only
 // 32-bit registers are valid arguments.
 void HexagonTfrCleanup::setReg(unsigned R32, uint32_t V32, ImmediateMap &IMap) {
-  ImmediateMap::iterator F = IMap.find(R32);
-  if (F == IMap.end())
-    IMap.insert(std::make_pair(R32, V32));
-  else
-    F->second = V32;
+  IMap[R32] = V32;
 }
 
 // Retrieve a value of the provided register Reg and store it into Val.

>From 3c1a48fd424d2eed35bc8806ebf289fb3e022b79 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 8 Sep 2024 09:07:07 -0700
Subject: [PATCH 2/2] Use operator[].

---
 llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index f5f25523ca9d54..8cf853ad0110d1 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -297,9 +297,7 @@ LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
       unsigned Exec) {
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  auto [F, Inserted] = Map.try_emplace(RR.Reg, Mask);
-  if (!Inserted)
-    F->second |= Mask;
+  Map[RR.Reg] |= Mask;
 }
 
 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,