[llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #107760)

via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 8 08:13:17 PDT 2024


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-hexagon

Author: Kazu Hirata (kazutakahirata)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/107760.diff


2 Files Affected:

- (modified) llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp (+2-4) 
- (modified) llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp (+1-5) 


``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 88b4defc754ab1..f5f25523ca9d54 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -297,10 +297,8 @@ LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
       unsigned Exec) {
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  ReferenceMap::iterator F = Map.find(RR.Reg);
-  if (F == Map.end())
-    Map.insert(std::make_pair(RR.Reg, Mask));
-  else
+  auto [F, Inserted] = Map.try_emplace(RR.Reg, Mask);
+  if (!Inserted)
     F->second |= Mask;
 }
 
diff --git a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
index fe0875a3d6a4f3..e042522663867a 100644
--- a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
@@ -92,11 +92,7 @@ bool HexagonTfrCleanup::isIntReg(unsigned Reg, bool &Is32) {
 // Assign given value V32 to the specified the register R32 in the map. Only
 // 32-bit registers are valid arguments.
 void HexagonTfrCleanup::setReg(unsigned R32, uint32_t V32, ImmediateMap &IMap) {
-  ImmediateMap::iterator F = IMap.find(R32);
-  if (F == IMap.end())
-    IMap.insert(std::make_pair(R32, V32));
-  else
-    F->second = V32;
+  IMap[R32] = V32;
 }
 
 // Retrieve a value of the provided register Reg and store it into Val.

``````````

</details>


https://github.com/llvm/llvm-project/pull/107760


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