[llvm] 11eae67 - [ARM] Add and extend big-endian testing for vorrimm and vbicimm. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 7 07:36:59 PDT 2024
Author: David Green
Date: 2024-09-07T15:36:54+01:00
New Revision: 11eae671b707618ad09915ecac3f910e3874b1af
URL: https://github.com/llvm/llvm-project/commit/11eae671b707618ad09915ecac3f910e3874b1af
DIFF: https://github.com/llvm/llvm-project/commit/11eae671b707618ad09915ecac3f910e3874b1af.diff
LOG: [ARM] Add and extend big-endian testing for vorrimm and vbicimm. NFC
Added:
Modified:
llvm/test/CodeGen/ARM/big-endian-vmov.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 7e0947ccfd58e8..327d4334ad83a1 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -144,7 +144,7 @@ define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
;
; CHECK-BE-LABEL: vmov_i64_b:
; CHECK-BE: @ %bb.0:
-; CHECK-BE-NEXT: d16, #0xff0000ff00ffff00
+; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000ff00ffff00
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: bx lr
ret <1 x i64> <i64 72056498804490495>
@@ -180,7 +180,7 @@ define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
;
; CHECK-BE-LABEL: and_v2i64_b:
; CHECK-BE: @ %bb.0:
-; CHECK-BE-NEXT: q8, #0xff0000ff00ffff00
+; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
; CHECK-BE-NEXT: vrev64.32 q8, q8
; CHECK-BE-NEXT: vand q0, q0, q8
; CHECK-BE-NEXT: bx lr
@@ -219,6 +219,7 @@ define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
}
+; FIXME: This is incorrect for BE
define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
; CHECK-LE-LABEL: and_v8i16_m1:
; CHECK-LE: @ %bb.0:
@@ -236,6 +237,22 @@ define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
}
; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
+; CHECK-LE-LABEL: or_v8i16_1:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: vorr.i32 q0, #0x10000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: or_v8i16_1:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vrev64.32 q8, q0
+; CHECK-BE-NEXT: vorr.i32 q8, #0x10000
+; CHECK-BE-NEXT: vrev64.32 q0, q8
+; CHECK-BE-NEXT: bx lr
+ %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
+ ret <8 x i16> %b
+}
+
define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {
; CHECK-LE-LABEL: xor_v8i16_m1:
; CHECK-LE: @ %bb.0:
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
index 54bbb0d48643c3..3399d62ff13460 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
@@ -1,61 +1,104 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh0(<8 x i16> %a) {
-; CHECK-LABEL: test_vbicq_n_u16_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i16 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u16_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i16 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u16_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vbic.i16 q1, #0x64
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101>
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh8(<8 x i16> %a) {
-; CHECK-LABEL: test_vbicq_n_u16_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i16 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u16_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i16 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u16_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vbic.i16 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601>
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh0(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i32 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i32 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vbic.i32 q1, #0x64
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh8(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i32 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i32 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vbic.i32 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh16(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i32 q0, #0x640000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh16:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i32 q0, #0x640000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh16:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vbic.i32 q1, #0x640000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh24(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_sh24:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vbic.i32 q0, #0x64000000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_sh24:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vbic.i32 q0, #0x64000000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_sh24:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vbic.i32 q1, #0x64000000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601>
ret <4 x i32> %0
@@ -65,83 +108,142 @@ entry:
; so in this case we expect to see the constant being prepared in
; another register.
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_illegal(<4 x i32> %a) {
-; CHECK-LABEL: test_vbicq_n_u32_illegal:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmvn.i32 q1, #0x54ff
-; CHECK-NEXT: vand q0, q0, q1
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_n_u32_illegal:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmvn.i32 q1, #0x54ff
+; CHECK-LE-NEXT: vand q0, q0, q1
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_n_u32_illegal:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmvn.i32 q0, #0x54ff
+; CHECK-BE-NEXT: vand q1, q1, q0
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = and <4 x i32> %a, <i32 -21760, i32 -21760, i32 -21760, i32 -21760>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh0(<8 x i16> %a) {
-; CHECK-LABEL: test_vorrq_n_u16_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i16 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u16_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i16 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u16_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vorr.i16 q1, #0x64
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100>
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh8(<8 x i16> %a) {
-; CHECK-LABEL: test_vorrq_n_u16_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i16 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u16_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i16 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u16_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vorr.i16 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600>
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh0(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i32 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i32 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vorr.i32 q1, #0x64
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh8(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i32 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i32 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vorr.i32 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh16(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i32 q0, #0x640000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh16:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i32 q0, #0x640000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh16:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vorr.i32 q1, #0x640000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh24(<4 x i32> %a) {
-; CHECK-LABEL: test_vorrq_n_u32_sh24:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vorr.i32 q0, #0x64000000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_n_u32_sh24:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vorr.i32 q0, #0x64000000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_n_u32_sh24:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vorr.i32 q1, #0x64000000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600>
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u16_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i16 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i16 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i16 q1, #0x64
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -151,12 +253,21 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u16_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i16 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u16_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i16 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u16_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i16 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -166,12 +277,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i32 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i32 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i32 q1, #0x64
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -181,12 +301,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i32 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i32 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i32 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -196,12 +325,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i32 q0, #0x640000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh16:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i32 q0, #0x640000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh16:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i32 q1, #0x640000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -211,12 +349,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vbicq_m_n_u32_sh24:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vbict.i32 q0, #0x64000000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vbicq_m_n_u32_sh24:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vbict.i32 q0, #0x64000000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vbicq_m_n_u32_sh24:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vbict.i32 q1, #0x64000000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -226,12 +373,21 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u16_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i16 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i16 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i16 q1, #0x64
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -241,12 +397,21 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u16_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i16 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u16_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i16 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u16_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i16 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -256,12 +421,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh0:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i32 q0, #0x64
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh0:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i32 q0, #0x64
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh0:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i32 q1, #0x64
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -271,12 +445,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh8:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i32 q0, #0x6400
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh8:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i32 q0, #0x6400
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh8:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i32 q1, #0x6400
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -286,12 +469,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i32 q0, #0x640000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh16:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i32 q0, #0x640000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh16:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i32 q1, #0x640000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -301,12 +493,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) {
-; CHECK-LABEL: test_vorrq_m_n_u32_sh24:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vorrt.i32 q0, #0x64000000
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vorrq_m_n_u32_sh24:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vorrt.i32 q0, #0x64000000
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vorrq_m_n_u32_sh24:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vorrt.i32 q1, #0x64000000
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
@@ -334,12 +535,21 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> %inactive, i16 zeroext %p) {
-; CHECK-LABEL: test_vmvnq_m_n_u16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vmvnt.i16 q0, #0xaa00
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vmvnq_m_n_u16:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vmvnt.i16 q0, #0xaa00
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vmvnq_m_n_u16:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vmvnt.i16 q1, #0xaa00
+; CHECK-BE-NEXT: vrev64.16 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
@@ -348,12 +558,21 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_u32(<4 x i32> %inactive, i16 zeroext %p) {
-; CHECK-LABEL: test_vmvnq_m_n_u32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmsr p0, r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vmvnt.i32 q0, #0xaa00
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: test_vmvnq_m_n_u32:
+; CHECK-LE: @ %bb.0: @ %entry
+; CHECK-LE-NEXT: vmsr p0, r0
+; CHECK-LE-NEXT: vpst
+; CHECK-LE-NEXT: vmvnt.i32 q0, #0xaa00
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_vmvnq_m_n_u32:
+; CHECK-BE: @ %bb.0: @ %entry
+; CHECK-BE-NEXT: vrev64.32 q1, q0
+; CHECK-BE-NEXT: vmsr p0, r0
+; CHECK-BE-NEXT: vpst
+; CHECK-BE-NEXT: vmvnt.i32 q1, #0xaa00
+; CHECK-BE-NEXT: vrev64.32 q0, q1
+; CHECK-BE-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index fe63034c7acd37..9cf92663e3b052 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -1050,7 +1050,6 @@ entry:
ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
}
-; FIXME: This is incorrect for BE
define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
; CHECKLE: @ %bb.0: @ %entry
@@ -1331,3 +1330,37 @@ entry:
%s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s
}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
+; CHECKLE-LABEL: and_v8i16_m1:
+; CHECKLE: @ %bb.0:
+; CHECKLE-NEXT: vbic.i32 q0, #0x10000
+; CHECKLE-NEXT: bx lr
+;
+; CHECKBE-LABEL: and_v8i16_m1:
+; CHECKBE: @ %bb.0:
+; CHECKBE-NEXT: vrev64.32 q1, q0
+; CHECKBE-NEXT: vbic.i32 q1, #0x10000
+; CHECKBE-NEXT: vrev64.32 q0, q1
+; CHECKBE-NEXT: bx lr
+ %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
+ ret <8 x i16> %b
+}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
+; CHECKLE-LABEL: or_v8i16_1:
+; CHECKLE: @ %bb.0:
+; CHECKLE-NEXT: vorr.i32 q0, #0x10000
+; CHECKLE-NEXT: bx lr
+;
+; CHECKBE-LABEL: or_v8i16_1:
+; CHECKBE: @ %bb.0:
+; CHECKBE-NEXT: vrev64.32 q1, q0
+; CHECKBE-NEXT: vorr.i32 q1, #0x10000
+; CHECKBE-NEXT: vrev64.32 q0, q1
+; CHECKBE-NEXT: bx lr
+ %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
+ ret <8 x i16> %b
+}
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