[llvm] [WIP] [IR] Add `llvm.sincos` intrinsic (PR #107639)

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git-clang-format --diff 865edb0436bc55a3df3596eefb9a83050a5c7a96 9265c94050fefeb071215e9e9b4ce2fe1fd358d1 --extensions cpp,h -- llvm/include/llvm/CodeGen/BasicTTIImpl.h llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
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diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 800addb39b..27e301902f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -2728,8 +2728,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
     case ISD::FFREXP:     R = PromoteFloatRes_FFREXP(N); break;
 
     case ISD::FSINCOS:
-                          R = PromoteFloatRes_FSINCOS(N);
-                          break;
+      R = PromoteFloatRes_FSINCOS(N);
+      break;
 
     case ISD::FP_ROUND:   R = PromoteFloatRes_FP_ROUND(N); break;
     case ISD::STRICT_FP_ROUND:
@@ -3352,8 +3352,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FSINCOS(SDNode *N) {
 
   // Promote to the larger FP type.
   Op = DAG.getNode(GetPromotionOpcode(OVT, NVT), dl, NVT, Op);
-  SDValue Res = DAG.getNode(N->getOpcode(), dl,
-                            DAG.getVTList(NVT, NVT), Op);
+  SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(NVT, NVT), Op);
 
   // Convert back to FP16 as an integer.
   ISD::NodeType Truncate = GetPromotionOpcode(NVT, OVT);

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https://github.com/llvm/llvm-project/pull/107639