[llvm] [PowerPC] Utilize `getReservedRegs` to find asm clobberable registers. (PR #99766)

[zhijian lin via llvm-commits]

================
@@ -341,7 +341,9 @@ def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
   // This also helps setting the correct `NumOfGPRsSaved' in traceback table.
   let AltOrders = [(add (sub GPRC, R2), R2),
                    (add (sequence "R%u", 2, 12),
-                        (sequence "R%u", 31, 13), R0, R1, FP, BP)];
+                        (sequence "R%u", 31, 13), R0, R1, FP, BP),
+                   (add (sequence "R%u", 3, 12),
+                        (sequence "R%u", 31, 13), R2, R0, R1, FP, BP)];
----------------
diggerlin wrote:

from the function 
 ```
 unsigned getGPRAllocationOrderIdx() const {
    if (is64BitELFABI())
      return 1;
    if (isAIXABI())
      return IsPPC64 ? 3 : 2;
    return 0;
  }

```

32-bit target will use the 

```
add (sequence "R%u", 2, 12),
                        (sequence "R%u", 31, 13), R0, R1, FP, BP),
```
                        
64-bit will use 

```
add (sequence "R%u", 3, 12),
                        (sequence "R%u", 31, 13), R2, R0, R1, FP, BP)   
```             

not sure why R2 is highest in 32bit , but 64-bit is not ?


https://github.com/llvm/llvm-project/pull/99766