[llvm] c1f78d3 - [X86] LowerSELECTWithCmpZero - add missing description of fold and cleanup zero/allones extension code. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-09-06T17:37:01+01:00
New Revision: c1f78d349704c4a6be6abb436687f3ce449d3778

URL: https://github.com/llvm/llvm-project/commit/c1f78d349704c4a6be6abb436687f3ce449d3778
DIFF: https://github.com/llvm/llvm-project/commit/c1f78d349704c4a6be6abb436687f3ce449d3778.diff

LOG: [X86] LowerSELECTWithCmpZero - add missing description of fold and cleanup zero/allones extension code. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 44592afcf7216c..e20633e041072f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24084,13 +24084,13 @@ static SDValue LowerSELECTWithCmpZero(SDValue CmpVal, SDValue LHS, SDValue RHS,
   if (!CmpVT.isScalarInteger() || !VT.isScalarInteger())
     return SDValue();
 
+  // Convert OR/XOR 'identity' patterns (iff X is 0 or 1):
+  // select (X != 0), Y, (OR Y, Z) -> (OR Y, (AND (0 - X), Z))
+  // select (X != 0), Y, (XOR Y, Z) -> (XOR Y, (AND (0 - X), Z))
   if (!Subtarget.canUseCMOV() && X86CC == X86::COND_E &&
       CmpVal.getOpcode() == ISD::AND && isOneConstant(CmpVal.getOperand(1))) {
     SDValue Src1, Src2;
-    // true if RHS is XOR or OR operator and one of its operands
-    // is equal to LHS
-    // ( a , a op b) || ( b , a op b)
-    auto isOrXorPattern = [&]() {
+    auto isIdentityPattern = [&]() {
       if ((RHS.getOpcode() == ISD::XOR || RHS.getOpcode() == ISD::OR) &&
           (RHS.getOperand(0) == LHS || RHS.getOperand(1) == LHS)) {
         Src1 = RHS.getOperand(RHS.getOperand(0) == LHS ? 1 : 0);
@@ -24100,20 +24100,17 @@ static SDValue LowerSELECTWithCmpZero(SDValue CmpVal, SDValue LHS, SDValue RHS,
       return false;
     };
 
-    if (isOrXorPattern()) {
-      SDValue Neg;
-      unsigned int CmpSz = CmpVT.getSizeInBits();
+    if (isIdentityPattern()) {
       // we need mask of all zeros or ones with same size of the other
       // operands.
-      if (CmpSz > VT.getSizeInBits())
+      SDValue Neg = CmpVal;
+      if (CmpVT.bitsGT(VT))
         Neg = DAG.getNode(ISD::TRUNCATE, DL, VT, CmpVal);
-      else if (CmpSz < VT.getSizeInBits())
+      else if (CmpVT.bitsLT(VT))
         Neg = DAG.getNode(
             ISD::AND, DL, VT,
             DAG.getNode(ISD::ANY_EXTEND, DL, VT, CmpVal.getOperand(0)),
             DAG.getConstant(1, DL, VT));
-      else
-        Neg = CmpVal;
       SDValue Mask = DAG.getNegative(Neg, DL, VT); // -(and (x, 0x1))
       SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
       return DAG.getNode(RHS.getOpcode(), DL, VT, And, Src2);  // And Op y