[llvm] 62180df - [RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 6 09:28:37 PDT 2024
Author: Craig Topper
Date: 2024-09-06T09:28:33-07:00
New Revision: 62180dfd8d86af92219662d0cdb01672d801f86f
URL: https://github.com/llvm/llvm-project/commit/62180dfd8d86af92219662d0cdb01672d801f86f
DIFF: https://github.com/llvm/llvm-project/commit/62180dfd8d86af92219662d0cdb01672d801f86f.diff
LOG: [RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
DataLayout, ABI, and TargetLowering can all be obtained via the
MachineFunction reference in the State object. This is how the targets
that use TableGen for CC handlers get these objects.
This might be a little slower, but it simplies all the callers in
SelectionDAG and GlobalISel.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
llvm/lib/Target/RISCV/RISCVCallingConv.cpp
llvm/lib/Target/RISCV/RISCVCallingConv.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 14832204058f88..f50611aac5dd1f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -45,13 +45,8 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
- MachineFunction &MF = State.getMachineFunction();
- const DataLayout &DL = MF.getDataLayout();
- const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
-
- if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
- LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
- *Subtarget.getTargetLowering()))
+ if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State, Info.IsFixed,
+ IsRet, Info.Ty))
return true;
StackSize = State.getStackSize();
@@ -197,15 +192,12 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
MachineFunction &MF = State.getMachineFunction();
- const DataLayout &DL = MF.getDataLayout();
- const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
if (LocVT.isScalableVector())
MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
- if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
- LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
- *Subtarget.getTargetLowering()))
+ if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State,
+ /*IsFixed=*/true, IsRet, Info.Ty))
return true;
StackSize = State.getStackSize();
@@ -441,11 +433,9 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
SmallVectorImpl<BaseArgInfo> &Outs,
bool IsVarArg) const {
SmallVector<CCValAssign, 16> ArgLocs;
- const auto &TLI = *getTLI<RISCVTargetLowering>();
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
MF.getFunction().getContext());
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
std::optional<unsigned> FirstMaskArgument = std::nullopt;
@@ -460,9 +450,8 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
MVT VT = MVT::getVT(Outs[I].Ty);
- if (CC_RISCV(MF.getDataLayout(), ABI, I, VT, VT, CCValAssign::Full,
- Outs[I].Flags[0], CCInfo, /*IsFixed=*/true,
- /*isRet=*/true, nullptr, TLI))
+ if (CC_RISCV(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo,
+ /*IsFixed=*/true, /*isRet=*/true, nullptr))
return false;
}
return true;
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index bf6ae2d1c29102..48f91bba090446 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -247,10 +247,14 @@ static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo, CCState &State,
}
// Implements the RISC-V calling convention. Returns true upon failure.
-bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI) {
+bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
+ const MachineFunction &MF = State.getMachineFunction();
+ const DataLayout &DL = MF.getDataLayout();
+ const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
+
unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
assert(XLen == 32 || XLen == 64);
MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
@@ -276,6 +280,7 @@ bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// variadic argument, or if no F64 argument registers are available.
bool UseGPRForF64 = true;
+ RISCVABI::ABI ABI = Subtarget.getTargetABI();
switch (ABI) {
default:
llvm_unreachable("Unexpected ABI");
@@ -502,12 +507,15 @@ bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// FastCC has less than 1% performance improvement for some particular
// benchmark. But theoretically, it may have benefit for some cases.
-bool llvm::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
- unsigned ValNo, MVT ValVT, MVT LocVT,
+bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State,
- bool IsFixed, bool IsRet, Type *OrigTy,
- const RISCVTargetLowering &TLI) {
+ bool IsFixed, bool IsRet, Type *OrigTy) {
+ const MachineFunction &MF = State.getMachineFunction();
+ const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
+ RISCVABI::ABI ABI = Subtarget.getTargetABI();
+
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@@ -515,8 +523,6 @@ bool llvm::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
}
}
- const RISCVSubtarget &Subtarget = TLI.getSubtarget();
-
if (LocVT == MVT::f16 && Subtarget.hasStdExtZfhmin()) {
static const MCPhysReg FPR16List[] = {
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H, RISCV::F14_H,
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.h b/llvm/lib/Target/RISCV/RISCVCallingConv.h
index 9154a31d116089..bf823b78317d54 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.h
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.h
@@ -15,28 +15,21 @@
namespace llvm {
-class DataLayout;
-class RISCVTargetLowering;
-
/// RISCVCCAssignFn - This target-specific function extends the default
/// CCValAssign with additional information used to lower RISC-V calling
/// conventions.
-typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
- unsigned ValNo, MVT ValVT, MVT LocVT,
+typedef bool RISCVCCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State,
- bool IsFixed, bool IsRet, Type *OrigTy,
- const RISCVTargetLowering &TLI);
-
-bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
-
-bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
+ bool IsFixed, bool IsRet, Type *OrigTy);
+
+bool CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
+
+bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b0c8c95d67cdea..3ef13b648493e7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18951,9 +18951,8 @@ void RISCVTargetLowering::analyzeInputArgs(
else if (Ins[i].isOrigArg())
ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
- ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this)) {
+ if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+ /*IsFixed=*/true, IsRet, ArgTy)) {
LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
<< ArgVT << '\n');
llvm_unreachable(nullptr);
@@ -18972,9 +18971,8 @@ void RISCVTargetLowering::analyzeOutputArgs(
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
- ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this)) {
+ if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+ Outs[i].IsFixed, IsRet, OrigTy)) {
LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
<< ArgVT << "\n");
llvm_unreachable(nullptr);
@@ -19688,10 +19686,8 @@ bool RISCVTargetLowering::CanLowerReturn(
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
MVT VT = Outs[i].VT;
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
- ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr,
- *this))
+ if (CC_RISCV(i, VT, VT, CCValAssign::Full, ArgFlags, CCInfo,
+ /*IsFixed=*/true, /*IsRet=*/true, nullptr))
return false;
}
return true;
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