[llvm] [ARM][Codegen] Fix vector data miscompilation in arm32be (PR #105519)

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git-clang-format --diff dff3c9614144012afc51e0d5455512e4974c6ced e9682f0f8acdfa5324fd2263efb99381a1fda2e7 --extensions cpp -- llvm/lib/Target/ARM/ARMISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 8a70d2094e..2d3cde92f9 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -18584,7 +18584,7 @@ static SDValue PerformBITCASTCombine(SDNode *N,
   // combine performed on it, so skip past any VECTOR_REG_CASTs.
   if (Src.getOpcode() == ARMISD::VECTOR_REG_CAST &&
       Src.getOperand(0).getValueType().getScalarSizeInBits() <=
-      Src.getValueType().getScalarSizeInBits())
+          Src.getValueType().getScalarSizeInBits())
     Src = Src.getOperand(0);
 
   // Bitcast from element-wise VMOV or VMVN doesn't need VREV if the VREV that

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https://github.com/llvm/llvm-project/pull/105519