[llvm] [AMDGPU][MC] Disallow null as saddr in flat instructions (PR #101730)

[Matt Arsenault via llvm-commits]

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@@ -6205,6 +6205,12 @@ void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
     return;
 
   Register ToSGPR = readlaneVGPRToSGPR(SAddr->getReg(), MI, MRI);
+
+  const TargetRegisterClass *DeclaredRC =
+      getRegClass(MI.getDesc(), SAddr->getOperandNo(),
+                  MRI.getTargetRegisterInfo(), *MI.getParent()->getParent());
+
+  MRI.setRegClass(ToSGPR, DeclaredRC);
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arsenm wrote:

This is the wrong way to fix this. readlaneVGPRToSGPR can already check the operand class directly, and then apply getCommonSubClass to the most general result getSGPRClassForBitWidth returned. You shouldn't let it create the wrong register class and then redo it after 

https://github.com/llvm/llvm-project/pull/101730