[llvm] [SandboxVec] Boilerplate (PR #107431)

[Arthur Eubanks via llvm-commits]

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@@ -0,0 +1,60 @@
+//===- SandboxVectorizer.cpp - Vectorizer based on Sandbox IR -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h"
+#include "llvm/Support/CommandLine.h"
+
+using namespace llvm;
+
+#define SV_NAME "sandbox-vectorizer"
+#define DEBUG_TYPE "SBVec"
+
+cl::opt<bool>
+    SBVecDisable("sbvec-disable", cl::init(false), cl::Hidden,
+                 cl::desc("Disable the Sandbox Vectorization passes"));
+
+PreservedAnalyses SandboxVectorizerPass::run(Function &F,
+                                             FunctionAnalysisManager &AM) {
+  TTI = &AM.getResult<TargetIRAnalysis>(F);
+
+  bool Changed = runImpl(F);
+  if (!Changed)
+    return PreservedAnalyses::all();
+
+  PreservedAnalyses PA;
+  PA.preserveSet<CFGAnalyses>();
+  return PA;
+}
+
+bool SandboxVectorizerPass::runImpl(Function &F) {
+  if (SBVecDisable)
+    return false;
+
+  // If the target claims to have no vector registers don't attempt
+  // vectorization.
+  if (!TTI->getNumberOfRegisters(TTI->getRegisterClassForType(true))) {
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aeubanks wrote:

I'd add this (and below) logic alongside tests later

https://github.com/llvm/llvm-project/pull/107431