[llvm] [AArch64] Prevent generating tbl instruction instead of smull (PR #106375)

[Igor Kirillov via llvm-commits]

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@@ -16795,6 +16795,16 @@ bool AArch64TargetLowering::optimizeExtendOrTruncateConversion(
 
       DstTy = TruncDstType;
     }
+
+    // mul(zext(i8), sext) can be transformed into smull(zext, sext) when
+    // destination type is at least SrcWidth * 4, which is faster than using tbl
+    // instructions
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igogo-x86 wrote:

@fhahn, as far as I understand, `AArch64TTI::isWideningInstruction` returns true only if all ZExt/SExt gets removed, but in our case, only one step of widening can be skipped:

> // Return true if the legalized types have the same number of vector elements
> // and the destination element type size is twice that of the source type.

Our case can be called partially widening, but I am not sure it is a good function to create.

https://github.com/llvm/llvm-project/pull/106375