[llvm] [AArch64]Fix invalid use of ld1/st1 in stack alloc (PR #105518)

[Sander de Smalen via llvm-commits]

================
@@ -3355,8 +3360,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
           MachineMemOperand::MOStore, Size, Alignment));
       MIB.addReg(PnReg);
       MIB.addReg(AArch64::SP)
-          .addImm(RPI.Offset) // [sp, #offset*scale],
-                              // where factor*scale is implicit
+          .addImm(RPI.Offset / 2) // [sp, #offset*2*scale],
+                                  // where scale is implicit
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sdesmalen-arm wrote:

I read 'offset' as meaning the actual encoded immediate `RPI.Offset / 2`, because (along with the SP reg that is added on the line above), that is the MachineInstr that is being built here. The semantics of the encoded address is then `[sp, #offset * 2 * vscale]`, where `2 * vscale` is implied by the instruction, which is what I think the comment tries to clarify.

What about replacing `#offset` by `#imm`, such that we end up with:
```
// [sp, #imm*2*vscale]
// where 2*vscale is implicit
```
?

https://github.com/llvm/llvm-project/pull/105518