[llvm] [NewPM][CodeGen] Port MachineLICM to NPM (PR #107376)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 03:21:55 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-debuginfo
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-backend-x86
Author: Akshat Oke (Akshat-Oke)
<details>
<summary>Changes</summary>
---
Patch is 38.33 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/107376.diff
20 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineBasicBlock.h (+6-6)
- (added) llvm/include/llvm/CodeGen/MachineLICM.h (+33)
- (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+1)
- (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+2-2)
- (modified) llvm/lib/CodeGen/MachineLICM.cpp (+116-58)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1)
- (modified) llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/licm-regpressure.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/licm-valu.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir (+1)
- (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir (+17-1)
- (modified) llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir (+16-1)
- (modified) llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir (+2-1)
- (modified) llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir (+1)
- (modified) llvm/test/CodeGen/X86/unfoldMemoryOperand.mir (+2-1)
- (modified) llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir (+1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 6efb17c55493a9..6cf151c951b19f 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -983,6 +983,12 @@ class MachineBasicBlock
return SplitCriticalEdge(Succ, nullptr, &MFAM, LiveInSets);
}
+ // Helper method for new pass manager migration.
+ MachineBasicBlock *
+ SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
+ MachineFunctionAnalysisManager *MFAM,
+ std::vector<SparseBitVector<>> *LiveInSets);
+
/// Check if the edge between this block and the given successor \p
/// Succ, can be split. If this returns true a subsequent call to
/// SplitCriticalEdge is guaranteed to return a valid basic block if
@@ -1256,12 +1262,6 @@ class MachineBasicBlock
/// unless you know what you're doing, because it doesn't update Pred's
/// successors list. Use Pred->removeSuccessor instead.
void removePredecessor(MachineBasicBlock *Pred);
-
- // Helper method for new pass manager migration.
- MachineBasicBlock *
- SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
- MachineFunctionAnalysisManager *MFAM,
- std::vector<SparseBitVector<>> *LiveInSets);
};
raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
new file mode 100644
index 00000000000000..7d3cd4d5135472
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -0,0 +1,33 @@
+
+//===- llvm/CodeGen/MachineLICM.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINELICM_H
+#define LLVM_CODEGEN_MACHINELICM_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+template <typename DerivedT, bool PreRegAlloc>
+class MachineLICMBasePass : public PassInfoMixin<DerivedT> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+class EarlyMachineLICMPass
+ : public MachineLICMBasePass<EarlyMachineLICMPass, true> {};
+
+class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
+
+template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class MachineLICMBasePass<MachineLICMPass, false>;
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINELICM_H
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index a99fed86d168d1..13bc4700d87029 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -44,6 +44,7 @@
#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineVerifier.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 4047fd0478579f..bf3965d76c878a 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -133,6 +133,8 @@ MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass())
MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
+MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
+MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
@@ -203,7 +205,6 @@ DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass)
DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter)
DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass)
-DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass)
DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass)
@@ -227,7 +228,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
-DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 1e4bf4bba56220..e9b4c7679f7f2f 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@@ -117,7 +118,7 @@ STATISTIC(NumNotHoistedDueToHotness,
namespace {
enum HoistResult { NotHoisted = 1, Hoisted = 2, ErasedMI = 4 };
- class MachineLICMBase : public MachineFunctionPass {
+ class MachineLICMImpl {
const TargetInstrInfo *TII = nullptr;
const TargetLoweringBase *TLI = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -126,6 +127,8 @@ namespace {
TargetSchedModel SchedModel;
bool PreRegAlloc = false;
bool HasProfileData = false;
+ Pass *LegacyPass;
+ MachineFunctionAnalysisManager *MFAM;
// Various analyses that we use...
AliasAnalysis *AA = nullptr; // Alias analysis info.
@@ -182,22 +185,20 @@ namespace {
unsigned SpeculationState = SpeculateUnknown;
public:
- MachineLICMBase(char &PassID, bool PreRegAlloc)
- : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<MachineLoopInfoWrapperPass>();
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<AAResultsWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
+ MachineLICMImpl(bool PreRegAlloc, Pass *LegacyPass,
+ MachineFunctionAnalysisManager *MFAM, AliasAnalysis *AA,
+ MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *MLI,
+ MachineDominatorTree *DT)
+ : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM), AA(AA),
+ MBFI(MBFI), MLI(MLI), DT(DT) {
+ assert((LegacyPass || MFAM) && "LegacyPass or MFAM must be provided");
+ assert(!(LegacyPass && MFAM) &&
+ "LegacyPass and MFAM cannot be provided at the same time");
}
- void releaseMemory() override {
+ bool run(MachineFunction &MF);
+
+ void releaseMemory() {
RegSeen.clear();
RegPressure.clear();
RegLimit.clear();
@@ -297,6 +298,26 @@ namespace {
MachineBasicBlock *CurPreheader);
};
+ class MachineLICMBase : public MachineFunctionPass {
+ bool PreRegAlloc;
+
+ public:
+ MachineLICMBase(char &ID, bool PreRegAlloc)
+ : MachineFunctionPass(ID), PreRegAlloc(PreRegAlloc) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<MachineLoopInfoWrapperPass>();
+ if (DisableHoistingToHotterBlocks != UseBFI::None)
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ };
+
class MachineLICM : public MachineLICMBase {
public:
static char ID;
@@ -343,6 +364,19 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ MachineBlockFrequencyInfo *MBFI =
+ DisableHoistingToHotterBlocks != UseBFI::None
+ ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
+ : nullptr;
+ MachineLoopInfo *MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ MachineDominatorTree *DT =
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ MachineLICMImpl Impl(PreRegAlloc, this, nullptr, AA, MBFI, MLI, DT);
+ return Impl.run(MF);
+}
+
+bool MachineLICMImpl::run(MachineFunction &MF) {
Changed = FirstInLoop = false;
const TargetSubtargetInfo &ST = MF.getSubtarget();
TII = ST.getInstrInfo();
@@ -352,6 +386,11 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
+ // FIXME: Remove this assignment or convert to an assert?
+ // MachineLICM and PostRAMachineLICM were distinguished by introducing
+ // EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
+ // MRI::isSSA() check to determine whether register allocation has happened"
+ // (See 4a7c8e7).
PreRegAlloc = MRI->isSSA();
HasProfileData = MF.getFunction().hasProfileData();
@@ -371,13 +410,6 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
}
- // Get our Loop information...
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
if (HoistConstLoads)
InitializeLoadsHoistableLoops();
@@ -397,7 +429,7 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
CSEMap.clear();
}
}
-
+ releaseMemory();
return Changed;
}
@@ -478,7 +510,7 @@ static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
/// Examine the instruction for potential LICM candidate. Also
/// gather register def and frame object update information.
-void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
+void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
BitVector &RUClobbers,
SmallDenseSet<int> &StoredFIs,
SmallVectorImpl<CandidateInfo> &Candidates,
@@ -573,7 +605,7 @@ void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
/// Walk the specified region of the CFG and hoist loop invariants out to the
/// preheader.
-void MachineLICMBase::HoistRegionPostRA(MachineLoop *CurLoop,
+void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
if (!Preheader)
@@ -675,7 +707,7 @@ void MachineLICMBase::HoistRegionPostRA(MachineLoop *CurLoop,
/// Add register 'Reg' to the livein sets of BBs in the current loop, and make
/// sure it is not killed by any instructions in the loop.
-void MachineLICMBase::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
+void MachineLICMImpl::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
if (!BB->isLiveIn(Reg))
BB->addLiveIn(Reg);
@@ -692,7 +724,7 @@ void MachineLICMBase::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
/// When an instruction is found to only use loop invariant operands that is
/// safe to hoist, this instruction is called to do the dirty work.
-void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def,
+void MachineLICMImpl::HoistPostRA(MachineInstr *MI, unsigned Def,
MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
@@ -724,7 +756,7 @@ void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def,
/// Check if this mbb is guaranteed to execute. If not then a load from this mbb
/// may not be safe to hoist.
-bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB,
+bool MachineLICMImpl::IsGuaranteedToExecute(MachineBasicBlock *BB,
MachineLoop *CurLoop) {
if (SpeculationState != SpeculateUnknown)
return SpeculationState == SpeculateFalse;
@@ -748,7 +780,7 @@ bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB,
/// virtual register uses. Even though rematerializable RA might not actually
/// rematerialize it in this scenario. In that case we do not want to hoist such
/// instruction out of the loop in a belief RA will sink it back if needed.
-bool MachineLICMBase::isTriviallyReMaterializable(
+bool MachineLICMImpl::isTriviallyReMaterializable(
const MachineInstr &MI) const {
if (!TII->isTriviallyReMaterializable(MI))
return false;
@@ -761,14 +793,14 @@ bool MachineLICMBase::isTriviallyReMaterializable(
return true;
}
-void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
+void MachineLICMImpl::EnterScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
// Remember livein register pressure.
BackTrace.push_back(RegPressure);
}
-void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
+void MachineLICMImpl::ExitScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
BackTrace.pop_back();
}
@@ -776,9 +808,10 @@ void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
/// Destroy scope for the MBB that corresponds to the given dominator tree node
/// if its a leaf or all of its children are done. Walk up the dominator tree to
/// destroy ancestors which are now done.
-void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
- DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
- const DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
+void MachineLICMImpl::ExitScopeIfDone(
+ MachineDomTreeNode *Node,
+ DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren,
+ const DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap) {
if (OpenChildren[Node])
return;
@@ -796,7 +829,7 @@ void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
/// specified header block, and that are in the current loop) in depth first
/// order w.r.t the DominatorTree. This allows us to visit definitions before
/// uses, allowing us to hoist a loop body in one pass without iteration.
-void MachineLICMBase::HoistOutOfLoop(MachineDomTreeNode *HeaderN,
+void MachineLICMImpl::HoistOutOfLoop(MachineDomTreeNode *HeaderN,
MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
@@ -902,7 +935,7 @@ static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
/// Find all virtual register references that are liveout of the preheader to
/// initialize the starting "register pressure". Note this does not count live
/// through (livein but not used) registers.
-void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
+void MachineLICMImpl::InitRegPressure(MachineBasicBlock *BB) {
std::fill(RegPressure.begin(), RegPressure.end(), 0);
// If the preheader has only a single predecessor and it ends with a
@@ -921,7 +954,7 @@ void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
}
/// Update estimate of register pressure after the specified instruction.
-void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
+void MachineLICMImpl::UpdateRegPressure(const MachineInstr *MI,
bool ConsiderUnseenAsDef) {
auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/true, ConsiderUnseenAsDef);
for (const auto &RPIdAndCost : Cost) {
@@ -940,7 +973,7 @@ void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
/// figure out which usages are live-ins.
/// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
DenseMap<unsigned, int>
-MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
+MachineLICMImpl::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
bool ConsiderUnseenAsDef) {
DenseMap<unsigned, int> Cost;
if (MI->isImplicitDef())
@@ -1072,7 +1105,7 @@ static bool isCopyFeedingInvariantStore(const MachineInstr &MI,
/// Returns true if the instruction may be a suitable candidate for LICM.
/// e.g. If the instruction is a call, then it's obviously not safe to hoist it.
-bool MachineLICMBase::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
+bool MachineLICMImpl::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
// Check if it's safe to move the instruction.
bool DontMoveAcrossStore = !HoistConstLoads || !AllowedToHoistLoads[CurLoop];
if ((!I.isSafeToMove(DontMoveAcrossStore)) &&
@@ -1107,7 +1140,7 @@ bool MachineLICMBase::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
}
/// Returns true if the instruction is loop invariant.
-bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I,
+bool MachineLICMImpl::IsLoopInvariantInst(MachineInstr &I,
MachineLoop *CurLoop) {
if (!IsLICMCandidate(I, CurLoop)) {
LLVM_DEBUG(dbgs() << "LICM: Instruction not a LICM candidate\n");
@@ -1118,7 +1151,7 @@ bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I,
/// Return true if the specified instruction is used by a phi node and hoisting
/// it could cause a copy to be inserted.
-bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI,
+bool MachineLICMImpl::HasLoopPHIUse(const MachineInstr *MI,
MachineLoop *CurLoop) {
SmallVector<const MachineInstr *, 8> Work(1, MI);
do {
@@ -1152,7 +1185,7 @@ bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI,
/// Compute operand latency between a def of 'Reg' and an use in the current
/// loop, return true if the target considered it high.
-bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
+bool MachineLICMImpl::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
Register Reg,
MachineLoop *CurLoop) const {
if (MRI->use_nodbg_empty(Reg))
@@ -1184,7 +1217,7 @@ bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
/// Return true if the instruction is marked "cheap" or the operand latency
/// between its def and a use is one or less.
-bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
+bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
return true;
@@ -1209,9 +1242,8 @@ bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
/// Visit BBs from header to current BB, check if hoisting an instruction of the
/// given cost matrix can cause high register pressure.
-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/107376
More information about the llvm-commits
mailing list