[llvm] [NewPM][MachineLICM] Port MachineLICM to NPM (PR #107376)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 02:43:25 PDT 2024
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/107376
>From 6147b38d7d2039f3221fbb7436525f5e4992d4af Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 5 Sep 2024 09:33:59 +0000
Subject: [PATCH] [NewPM][MachineLICM] Port MachineLICM to NPM
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 12 +-
llvm/include/llvm/CodeGen/MachineLICM.h | 33 +++++
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/MachineLICM.cpp | 113 +++++++++++++-----
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 1 +
.../AArch64/mlicm-stack-write-check.mir | 1 +
.../CodeGen/AArch64/sme-machine-licm-vg.mir | 1 +
llvm/test/CodeGen/AMDGPU/licm-regpressure.mir | 1 +
llvm/test/CodeGen/AMDGPU/licm-valu.mir | 1 +
.../CodeGen/AMDGPU/machinelicm-convergent.mir | 1 +
.../AMDGPU/machinelicm-copy-like-instrs.mir | 1 +
.../CodeGen/AMDGPU/machinelicm-undef-use.mir | 1 +
...HoistingDueToBlockHotnessNoProfileData.mir | 18 ++-
...leHoistingDueToBlockHotnessProfileData.mir | 17 ++-
.../PowerPC/machinelicm-cse-dead-flag.mir | 3 +-
.../CodeGen/X86/machine-licm-vs-wineh.mir | 1 +
llvm/test/CodeGen/X86/unfoldMemoryOperand.mir | 3 +-
.../MIR/X86/mlicm-hoist-pre-regalloc.mir | 1 +
20 files changed, 175 insertions(+), 40 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/MachineLICM.h
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 6efb17c55493a9..6cf151c951b19f 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -983,6 +983,12 @@ class MachineBasicBlock
return SplitCriticalEdge(Succ, nullptr, &MFAM, LiveInSets);
}
+ // Helper method for new pass manager migration.
+ MachineBasicBlock *
+ SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
+ MachineFunctionAnalysisManager *MFAM,
+ std::vector<SparseBitVector<>> *LiveInSets);
+
/// Check if the edge between this block and the given successor \p
/// Succ, can be split. If this returns true a subsequent call to
/// SplitCriticalEdge is guaranteed to return a valid basic block if
@@ -1256,12 +1262,6 @@ class MachineBasicBlock
/// unless you know what you're doing, because it doesn't update Pred's
/// successors list. Use Pred->removeSuccessor instead.
void removePredecessor(MachineBasicBlock *Pred);
-
- // Helper method for new pass manager migration.
- MachineBasicBlock *
- SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
- MachineFunctionAnalysisManager *MFAM,
- std::vector<SparseBitVector<>> *LiveInSets);
};
raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
new file mode 100644
index 00000000000000..7d3cd4d5135472
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -0,0 +1,33 @@
+
+//===- llvm/CodeGen/MachineLICM.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINELICM_H
+#define LLVM_CODEGEN_MACHINELICM_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+template <typename DerivedT, bool PreRegAlloc>
+class MachineLICMBasePass : public PassInfoMixin<DerivedT> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+class EarlyMachineLICMPass
+ : public MachineLICMBasePass<EarlyMachineLICMPass, true> {};
+
+class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
+
+template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class MachineLICMBasePass<MachineLICMPass, false>;
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINELICM_H
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index a99fed86d168d1..13bc4700d87029 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -44,6 +44,7 @@
#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineVerifier.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 4047fd0478579f..bf3965d76c878a 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -133,6 +133,8 @@ MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass())
MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
+MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
+MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
@@ -203,7 +205,6 @@ DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass)
DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter)
DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass)
-DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass)
DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass)
@@ -227,7 +228,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
-DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 1e4bf4bba56220..9dd31e0fcea3cf 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@@ -117,7 +118,7 @@ STATISTIC(NumNotHoistedDueToHotness,
namespace {
enum HoistResult { NotHoisted = 1, Hoisted = 2, ErasedMI = 4 };
- class MachineLICMBase : public MachineFunctionPass {
+ class MachineLICMBase {
const TargetInstrInfo *TII = nullptr;
const TargetLoweringBase *TLI = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -126,6 +127,8 @@ namespace {
TargetSchedModel SchedModel;
bool PreRegAlloc = false;
bool HasProfileData = false;
+ Pass *LegacyPass;
+ MachineFunctionAnalysisManager *MFAM;
// Various analyses that we use...
AliasAnalysis *AA = nullptr; // Alias analysis info.
@@ -182,22 +185,20 @@ namespace {
unsigned SpeculationState = SpeculateUnknown;
public:
- MachineLICMBase(char &PassID, bool PreRegAlloc)
- : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<MachineLoopInfoWrapperPass>();
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<AAResultsWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
+ MachineLICMBase(bool PreRegAlloc, Pass *LegacyPass,
+ MachineFunctionAnalysisManager *MFAM, AliasAnalysis *AA,
+ MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *MLI,
+ MachineDominatorTree *DT)
+ : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM), AA(AA),
+ MBFI(MBFI), MLI(MLI), DT(DT) {
+ assert((LegacyPass || MFAM) && "LegacyPass or MFAM must be provided");
+ assert(!(LegacyPass && MFAM) &&
+ "LegacyPass and MFAM cannot be provided at the same time");
}
- void releaseMemory() override {
+ bool run(MachineFunction &MF);
+
+ void releaseMemory() {
RegSeen.clear();
RegPressure.clear();
RegLimit.clear();
@@ -296,19 +297,38 @@ namespace {
MachineBasicBlock *getCurPreheader(MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader);
};
+ class MachineLICMBaseLegacy : public MachineFunctionPass {
+ bool PreRegAlloc;
+
+ public:
+ MachineLICMBaseLegacy(char &ID, bool PreRegAlloc)
+ : MachineFunctionPass(ID), PreRegAlloc(PreRegAlloc) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<MachineLoopInfoWrapperPass>();
+ if (DisableHoistingToHotterBlocks != UseBFI::None)
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ };
- class MachineLICM : public MachineLICMBase {
+ class MachineLICM : public MachineLICMBaseLegacy {
public:
static char ID;
- MachineLICM() : MachineLICMBase(ID, false) {
+ MachineLICM() : MachineLICMBaseLegacy(ID, false) {
initializeMachineLICMPass(*PassRegistry::getPassRegistry());
}
};
- class EarlyMachineLICM : public MachineLICMBase {
+ class EarlyMachineLICM : public MachineLICMBaseLegacy {
public:
static char ID;
- EarlyMachineLICM() : MachineLICMBase(ID, true) {
+ EarlyMachineLICM() : MachineLICMBaseLegacy(ID, true) {
initializeEarlyMachineLICMPass(*PassRegistry::getPassRegistry());
}
};
@@ -339,10 +359,23 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm",
"Early Machine Loop Invariant Code Motion", false, false)
-bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
+bool MachineLICMBaseLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ MachineBlockFrequencyInfo *MBFI =
+ DisableHoistingToHotterBlocks != UseBFI::None
+ ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
+ : nullptr;
+ MachineLoopInfo *MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ MachineDominatorTree *DT =
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ MachineLICMBase Impl(PreRegAlloc, this, nullptr, AA, MBFI, MLI, DT);
+ return Impl.run(MF);
+}
+
+bool MachineLICMBase::run(MachineFunction &MF) {
Changed = FirstInLoop = false;
const TargetSubtargetInfo &ST = MF.getSubtarget();
TII = ST.getInstrInfo();
@@ -352,6 +385,11 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
+ // FIXME: Remove this assignment or convert to an assert?
+ // MachineLICM and PostRAMachineLICM were distinguished by introducing
+ // EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
+ // MRI::isSSA() check to determine whether register allocation has happened"
+ // (See 4a7c8e7).
PreRegAlloc = MRI->isSSA();
HasProfileData = MF.getFunction().hasProfileData();
@@ -371,13 +409,6 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
}
- // Get our Loop information...
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
if (HoistConstLoads)
InitializeLoadsHoistableLoops();
@@ -1704,7 +1735,8 @@ MachineLICMBase::getCurPreheader(MachineLoop *CurLoop,
return nullptr;
}
- CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), *this);
+ CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), LegacyPass,
+ MFAM, nullptr);
if (!CurPreheader) {
CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
return nullptr;
@@ -1731,3 +1763,28 @@ bool MachineLICMBase::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
// Compare the block frequency ratio with the threshold
return Ratio > BlockFrequencyRatioThreshold;
}
+
+template <typename DerivedT, bool PreRegAlloc>
+PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
+ MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getFunction().hasOptNone())
+ return PreservedAnalyses::all();
+
+ auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager();
+
+ auto *DT = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ auto *MLI = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ auto *MBFI = DisableHoistingToHotterBlocks != UseBFI::None
+ ? &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF)
+ : nullptr;
+ auto *AA = &FAM.getResult<AAManager>(MF.getFunction());
+
+ bool Changed =
+ MachineLICMBase(PreRegAlloc, nullptr, &MFAM, AA, MBFI, MLI, DT).run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index a22abed8051a11..512b667dbe852e 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -103,6 +103,7 @@
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachinePassManager.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 9c9c5051393730..6a62b4b2d85050 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -52,6 +52,7 @@
#include "llvm/CodeGen/GlobalISel/Localizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetPassConfig.h"
diff --git a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
index 0b1fdf9c33d66c..728598d97ebd19 100644
--- a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
+++ b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64 -run-pass machinelicm -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes machinelicm -verify-machineinstrs -o - %s | FileCheck %s
---
name: test
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir b/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
index e6cce9af0daf0e..6e9e353862d730 100644
--- a/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
+++ b/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=early-machinelicm %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -passes=early-machinelicm %s -verify-machineinstrs -o - | FileCheck %s
---
name: test_should_hoist_pfalse
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
index e818eaf95aee33..ac247b098e0d5e 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes machinelicm -o - %s | FileCheck -check-prefix=GCN %s
# MachineLICM shall limit hoisting of V_CVT instructions out of the loop keeping
# register pressure within the budget. VGPR budget at occupancy 10 is 24 vgprs.
diff --git a/llvm/test/CodeGen/AMDGPU/licm-valu.mir b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
index 00a5a4f1b32ea4..b4f5e057f532b5 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-valu.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machinelicm -o - %s | FileCheck -check-prefix=GCN %s
---
name: hoist_move
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
index e4ba07834405ac..9dc44c6e195e4c 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -o - %s | FileCheck %s
# Test to check machine LICM does not hoist convergent instructions,
# DS_PERMUTE_B32 in this example.
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
index e9945f005d2645..9465cc03209060 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -simplify-mir -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -simplify-mir -o - %s | FileCheck %s
# Test to check machine LICM does not hoist convergent instructions,
# DS_PERMUTE_B32 in this example.
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
index 07eaa9f95604d0..bdd08af1c7e160 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=early-machinelicm %s -o - | FileCheck %s
# Issue #100115: test that MachineLICM does not assert on the undef use operand
# of the REG_SEQUENCE instruction.
diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
index 9706873dc37fd6..99f607c89cbbd2 100644
--- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
+++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
@@ -16,7 +16,23 @@
# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=none \
# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
# RUN: --check-prefix=CHECK-HOIST
-
+#
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=all \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-NO-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=all \
+# RUN: -block-freq-ratio-threshold=100000000 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=none \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
--- |
target datalayout = "e-m:e-i64:64-n32:64"
diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
index 88ee6633c15feb..3372a0d8ec0b43 100644
--- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
+++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
@@ -15,7 +15,22 @@
# RUN: -disable-hoisting-to-hotter-blocks=none \
# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
# RUN: --check-prefix=CHECK-HOIST
-
+# Tests for the new pass manager
+# RUN: llc -passes early-machinelicm -verify-machineinstrs \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-NO-HOIST
+# RUN: llc -passes early-machinelicm -verify-machineinstrs \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100000000 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm -verify-machineinstrs \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=none \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
--- |
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
index 17913594003f51..462f5c74451e6a 100644
--- a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
+++ b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
@@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
----
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: %s -o - | FileCheck %s
name: deadFlagAfterCSE
# This case tests that after the dead %3 is CSE-ed with hoisted %5 in MachineLICM
# pass, the dead flag will be cleared for %3 if %5 has users.
diff --git a/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir b/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
index 4bfd749fb77235..3582b178869c4d 100644
--- a/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
+++ b/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
@@ -1,4 +1,5 @@
# RUN: llc -o - %s -mtriple=x86_64-pc-windows-msvc -run-pass=machinelicm | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64-pc-windows-msvc -passes=machinelicm | FileCheck %s
#
# This test checks that MachineLICM doesn't hoist loads out of funclets.
# Manually modified from the IR of the following C++ function by running
diff --git a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
index af57d972f22468..ff3d9ca378dbd5 100644
--- a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
+++ b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-- -run-pass machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-- -passes machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
--- |
@x = dso_local global i32 0, align 4
@z = dso_local local_unnamed_addr global [1024 x i32] zeroinitializer, align 16
diff --git a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
index 90a6abdf9bd0b3..d4d59e14724ebe 100644
--- a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
@@ -1,5 +1,6 @@
--- |
; RUN: llc -run-pass=machinelicm -o - %s | FileCheck %s
+ ; RUN: llc -passes=machinelicm -o - %s | FileCheck %s
; Line numbers should not be retained when loop invariant instructions are hoisted.
; Doing so causes poor stepping bevavior.
;
More information about the llvm-commits
mailing list