[llvm] [CodeGen][NewPM] Use verify-each option in npm tests (NFC). (PR #107373)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 02:32:14 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-aarch64
Author: Christudasan Devadasan (cdevadas)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/107373.diff
18 Files Affected:
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/cmp_shrink.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-multiple.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-true16.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/v_swap_b32.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir (+1-1)
- (modified) llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/cse-two-preds.mir (+1-1)
``````````diff
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
index 015ce5ec2dca60..9e9f7eb96665e7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
@@ -1,5 +1,5 @@
# RUN: llc -run-pass machine-cse -verify-machineinstrs -mtriple aarch64-apple-ios %s -o - | FileCheck %s
-# RUN: llc -passes machine-cse -mtriple aarch64-apple-ios %s -o - | FileCheck %s
+# RUN: llc -passes machine-cse -verify-each -mtriple aarch64-apple-ios %s -o - | FileCheck %s
---
name: irtranslated
legalized: false
diff --git a/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
index 9b3579b43a38a3..47266ed84fd61d 100644
--- a/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes si-shrink-instructions -verify-each %s -o - | FileCheck -check-prefix=GCN %s
---
name: not_shrink_icmp
diff --git a/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
index fee1391d150f98..f2cb13860e3ea9 100644
--- a/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -passes=machine-cse -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes=machine-cse -verify-each -o - %s | FileCheck %s
# Test to ensure that this does not crash on undefs
---
diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
index 919641f7e70d37..21f67dc9f525f0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
@@ -1,5 +1,5 @@
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
-# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-each -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
%f16.val0 = load volatile half, ptr addrspace(1) undef
diff --git a/llvm/test/CodeGen/AMDGPU/fold-multiple.mir b/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
index 9d992da0797755..d5ed63afc7ae72 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
@@ -1,5 +1,5 @@
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
-# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-each -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @test() #0 {
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir b/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
index 83adb93c9f41e6..6f70b1a281494c 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-each -passes=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
---
name: shrink_kimm32_mov_b32
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir b/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
index 6f5aa70649beee..1888331d92fcfe 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-each %s -o - | FileCheck %s
# Make sure immediate folding into V_CNDMASK respects constant bus restrictions.
---
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir b/llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
index b86767ba5585a8..42f3f3952765a3 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-each %s -o - | FileCheck -check-prefix=GCN %s
# Make sure the implicit vcc_lo of V_CNDMASK is preserved and not promoted to vcc.
---
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
index a8deda7ad95078..3c422e095a35ae 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-shrink-instructions -verify-each -o - %s | FileCheck %s
---
name: undef_and_operand_to_bitset0
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir b/llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
index ed2148ab5a1989..497b3a3856c9f7 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GFX10
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GFX11
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass si-shrink-instructions -verify-each %s -o - | FileCheck %s -check-prefixes=GFX11
---
name: mad_cvv_f32
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
index 1a7ec5db9efa2a..168693c76e0de9 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-shrink-instructions -verify-each -o - %s | FileCheck -check-prefix=GFX1100 %s
---
name: 16bit_lo128_shrink
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
index 9c74d94a1afefe..30eb40aa7b2747 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
@@ -1,5 +1,5 @@
# RUN: llc -verify-machineinstrs -mtriple=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -verify-machineinstrs -mtriple=amdgcn -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -verify-each -mtriple=amdgcn -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# Check that add with carry out isn't incorrectly reduced to e32 when
# the carry out is a virtual register.
diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
index 95aaea6ea80913..6eaca0fb002ac2 100644
--- a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
@@ -1,5 +1,5 @@
# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-each %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: swap_phys_condensed
# GCN: bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
index 7c032c2dc49724..5f267c47bd1684 100644
--- a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-each -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
--- |
define amdgpu_kernel void @fold_fi_vgpr() {
diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
index 292e96b4516fec..1c8cc62a58c40a 100644
--- a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
+++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-each -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: name: fold_imm_non_ssa{{$}}
# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
diff --git a/llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir b/llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
index 0e9459238ce9d7..5c31de4a8d7032 100644
--- a/llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
+++ b/llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -run-pass=machine-cse -verify-machineinstrs | FileCheck %s
-# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -passes=machine-cse | FileCheck %s
+# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -passes=machine-cse -verify-each | FileCheck %s
--- |
define void @can_pre() {
entry:
diff --git a/llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir b/llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
index cee5c24847f34a..e3b971f9215c43 100644
--- a/llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
+++ b/llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=machine-cse -o - %s | FileCheck %s
+# RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=machine-cse -verify-each -o - %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/X86/cse-two-preds.mir b/llvm/test/CodeGen/X86/cse-two-preds.mir
index e6f04a6ce66d43..a35f9701cd43a6 100644
--- a/llvm/test/CodeGen/X86/cse-two-preds.mir
+++ b/llvm/test/CodeGen/X86/cse-two-preds.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=x86_64 -verify-machineinstrs --run-pass=machine-cse -o - %s | FileCheck %s
-# RUN: llc -mtriple=x86_64 -passes=machine-cse -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -passes=machine-cse -verify-each -o - %s | FileCheck %s
--- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
``````````
</details>
https://github.com/llvm/llvm-project/pull/107373
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