[llvm] [Xtensa] Lowering FRAMEADDR/RETURNADDR operations. (PR #107363)

[Andrei Safronov via llvm-commits]

https://github.com/andreisfr updated https://github.com/llvm/llvm-project/pull/107363

>From a210ae9ea425993d5961497fbd68867dc91f64f1 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Thu, 5 Sep 2024 10:59:44 +0300
Subject: [PATCH] [Xtensa] Lowering FRAMEADDR/RETURNADDR operations.

---
 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 42 +++++++++++++++++++
 llvm/lib/Target/Xtensa/XtensaISelLowering.h   |  4 ++
 .../CodeGen/Xtensa/frameaddr-returnaddr.ll    | 22 ++++++++++
 3 files changed, 68 insertions(+)
 create mode 100644 llvm/test/CodeGen/Xtensa/frameaddr-returnaddr.ll

diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 0d2ce26a942e03..97d9c3e9f9f476 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -594,6 +594,26 @@ SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op,
                      FalseValue, TargetCC);
 }
 
+SDValue XtensaTargetLowering::LowerRETURNADDR(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  // check the depth
+  // TODO: xtensa-gcc can handle this, by navigating through the stack, we
+  // should be able to do this too
+  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
+         "Return address can be determined only for current frame.");
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+  EVT VT = Op.getValueType();
+  unsigned RA = Xtensa::A0;
+  MFI.setReturnAddressIsTaken(true);
+
+  // Return RA, which contains the return address. Mark it an implicit
+  // live-in.
+  unsigned Register = MF.addLiveIn(RA, getRegClassFor(MVT::i32));
+  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Register, VT);
+}
+
 SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
                                              SelectionDAG &DAG) const {
   const ConstantSDNode *CN = cast<ConstantSDNode>(Op);
@@ -722,6 +742,24 @@ SDValue XtensaTargetLowering::LowerSTACKRESTORE(SDValue Op,
                           Op.getOperand(1));
 }
 
+SDValue XtensaTargetLowering::LowerFRAMEADDR(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  // check the depth
+  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
+         "Frame address can only be determined for current frame.");
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
+  MFI.setFrameAddressIsTaken(true);
+  EVT VT = Op.getValueType();
+  SDLoc DL(Op);
+
+  unsigned FrameRegister = Subtarget.getRegisterInfo()->getFrameRegister(MF);
+  SDValue FrameAddr =
+      DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameRegister, VT);
+  return FrameAddr;
+}
+
 SDValue XtensaTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0); // Legalize the chain.
@@ -867,6 +905,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
     return LowerBR_JT(Op, DAG);
   case ISD::Constant:
     return LowerImmediate(Op, DAG);
+  case ISD::RETURNADDR:
+    return LowerRETURNADDR(Op, DAG);
   case ISD::GlobalAddress:
     return LowerGlobalAddress(Op, DAG);
   case ISD::BlockAddress:
@@ -883,6 +923,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
     return LowerSTACKSAVE(Op, DAG);
   case ISD::STACKRESTORE:
     return LowerSTACKRESTORE(Op, DAG);
+  case ISD::FRAMEADDR:
+    return LowerFRAMEADDR(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::SHL_PARTS:
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index 8e7346b40dfe59..2a878e45047d21 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -125,12 +125,16 @@ class XtensaTargetLowering : public TargetLowering {
 
   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
+
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
+
   SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
diff --git a/llvm/test/CodeGen/Xtensa/frameaddr-returnaddr.ll b/llvm/test/CodeGen/Xtensa/frameaddr-returnaddr.ll
new file mode 100644
index 00000000000000..69c22733c107ae
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/frameaddr-returnaddr.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare ptr @llvm.frameaddress(i32)
+declare ptr @llvm.returnaddress(i32)
+
+define ptr @test_frameaddress_0() nounwind {
+; CHECK-LABEL: test_frameaddress_0:
+; CHECK:         or a2, a1, a1
+; CHECK-NEXT:    ret
+  %1 = call ptr @llvm.frameaddress(i32 0)
+  ret ptr %1
+}
+
+define ptr @test_returnaddress_0() nounwind {
+; CHECK-LABEL: test_returnaddress_0:
+; CHECK:         or a2, a0, a0
+; CHECK-NEXT:    ret
+  %1 = call ptr @llvm.returnaddress(i32 0)
+  ret ptr %1
+}