[llvm] 0c1500e - [RISCV] Fix another RV32 Zdinx load/store addressing corner case.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-09-04T23:26:40-07:00
New Revision: 0c1500ef05e0a5b25cae79d2bd361dbc6e14e726

URL: https://github.com/llvm/llvm-project/commit/0c1500ef05e0a5b25cae79d2bd361dbc6e14e726
DIFF: https://github.com/llvm/llvm-project/commit/0c1500ef05e0a5b25cae79d2bd361dbc6e14e726.diff

LOG: [RISCV] Fix another RV32 Zdinx load/store addressing corner case.

RISCVExpandPseudoInsts makes sure the offset is divisible by 8
so we need to enforce that during isel.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 78006885421603..4580f3191d1389 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2691,7 +2691,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
           Align Alignment = commonAlignment(
               GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
           if ((CVal == 0 || Alignment > CVal) &&
-              (!IsRV32Zdinx || Alignment > (CVal + 4))) {
+              (!IsRV32Zdinx || commonAlignment(Alignment, CVal) > 4)) {
             int64_t CombinedOffset = CVal + GA->getOffset();
             Base = Base.getOperand(0);
             Offset = CurDAG->getTargetGlobalAddress(

diff  --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
index 01ecaee3d7e7b6..a4f56b6d28409c 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
@@ -493,3 +493,67 @@ entry:
   store double %d, ptr %add.ptr, align 8
   ret void
 }
+
+ at f = global double 4.2, align 16
+
+define double @foo13(ptr nocapture %p) nounwind {
+; RV32ZDINX-LABEL: foo13:
+; RV32ZDINX:       # %bb.0: # %entry
+; RV32ZDINX-NEXT:    addi sp, sp, -16
+; RV32ZDINX-NEXT:    lui a0, %hi(f)
+; RV32ZDINX-NEXT:    lw a1, %lo(f+8)(a0)
+; RV32ZDINX-NEXT:    sw a1, 12(sp)
+; RV32ZDINX-NEXT:    lw a0, %lo(f+4)(a0)
+; RV32ZDINX-NEXT:    sw a0, 8(sp)
+; RV32ZDINX-NEXT:    lw a0, 8(sp)
+; RV32ZDINX-NEXT:    lw a1, 12(sp)
+; RV32ZDINX-NEXT:    addi sp, sp, 16
+; RV32ZDINX-NEXT:    ret
+;
+; RV32ZDINXUALIGNED-LABEL: foo13:
+; RV32ZDINXUALIGNED:       # %bb.0: # %entry
+; RV32ZDINXUALIGNED-NEXT:    lui a0, %hi(f)
+; RV32ZDINXUALIGNED-NEXT:    addi a0, a0, %lo(f)
+; RV32ZDINXUALIGNED-NEXT:    lw a1, 8(a0)
+; RV32ZDINXUALIGNED-NEXT:    lw a0, 4(a0)
+; RV32ZDINXUALIGNED-NEXT:    ret
+;
+; RV64ZDINX-LABEL: foo13:
+; RV64ZDINX:       # %bb.0: # %entry
+; RV64ZDINX-NEXT:    lui a0, %hi(f)
+; RV64ZDINX-NEXT:    lwu a1, %lo(f+8)(a0)
+; RV64ZDINX-NEXT:    lwu a0, %lo(f+4)(a0)
+; RV64ZDINX-NEXT:    slli a1, a1, 32
+; RV64ZDINX-NEXT:    or a0, a1, a0
+; RV64ZDINX-NEXT:    ret
+entry:
+  %add.ptr = getelementptr inbounds i8, ptr @f, i64 4
+  %0 = load double, ptr %add.ptr, align 4
+  ret double %0
+}
+
+define double @foo14(ptr nocapture %p) nounwind {
+; RV32ZDINX-LABEL: foo14:
+; RV32ZDINX:       # %bb.0: # %entry
+; RV32ZDINX-NEXT:    lui a0, %hi(f)
+; RV32ZDINX-NEXT:    lw a1, %lo(f+12)(a0)
+; RV32ZDINX-NEXT:    lw a0, %lo(f+8)(a0)
+; RV32ZDINX-NEXT:    ret
+;
+; RV32ZDINXUALIGNED-LABEL: foo14:
+; RV32ZDINXUALIGNED:       # %bb.0: # %entry
+; RV32ZDINXUALIGNED-NEXT:    lui a0, %hi(f)
+; RV32ZDINXUALIGNED-NEXT:    lw a1, %lo(f+12)(a0)
+; RV32ZDINXUALIGNED-NEXT:    lw a0, %lo(f+8)(a0)
+; RV32ZDINXUALIGNED-NEXT:    ret
+;
+; RV64ZDINX-LABEL: foo14:
+; RV64ZDINX:       # %bb.0: # %entry
+; RV64ZDINX-NEXT:    lui a0, %hi(f)
+; RV64ZDINX-NEXT:    ld a0, %lo(f+8)(a0)
+; RV64ZDINX-NEXT:    ret
+entry:
+  %add.ptr = getelementptr inbounds i8, ptr @f, i64 8
+  %0 = load double, ptr %add.ptr, align 8
+  ret double %0
+}