[llvm] 1465e23 - [RISCV][llvm] Handle `ptr` element type in `lowerDeinterleaveIntrinsicToLoad` and `lowerInterleaveIntrinsicToStore` (#107079)
via llvm-commits
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Wed Sep 4 21:46:24 PDT 2024
Author: Brandon Wu
Date: 2024-09-05T12:46:20+08:00
New Revision: 1465e23985904d55a014f3377c287ded45c0fa0c
URL: https://github.com/llvm/llvm-project/commit/1465e23985904d55a014f3377c287ded45c0fa0c
DIFF: https://github.com/llvm/llvm-project/commit/1465e23985904d55a014f3377c287ded45c0fa0c.diff
LOG: [RISCV][llvm] Handle `ptr` element type in `lowerDeinterleaveIntrinsicToLoad` and `lowerInterleaveIntrinsicToStore` (#107079)
Resolve https://github.com/llvm/llvm-project/issues/106970
currently it returns 0 fixed size for `ptr` element type. The `ptr`
element size should depend on `XLen` which is 64 in riscv64 and 32 in
riscv32 respectively.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a9061a05c7c67f..d400b2ea1ca2ca 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21980,10 +21980,10 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(
VectorType *VTy = cast<VectorType>(DI->getOperand(0)->getType());
VectorType *ResVTy = cast<VectorType>(DI->getType()->getContainedType(0));
+ const DataLayout &DL = LI->getDataLayout();
if (!isLegalInterleavedAccessType(ResVTy, Factor, LI->getAlign(),
- LI->getPointerAddressSpace(),
- LI->getDataLayout()))
+ LI->getPointerAddressSpace(), DL))
return false;
Function *VlsegNFunc;
@@ -22005,7 +22005,7 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(
Intrinsic::riscv_vlseg6, Intrinsic::riscv_vlseg7,
Intrinsic::riscv_vlseg8};
- unsigned SEW = ResVTy->getElementType()->getScalarSizeInBits();
+ unsigned SEW = DL.getTypeSizeInBits(ResVTy->getElementType());
unsigned NumElts = ResVTy->getElementCount().getKnownMinValue();
Type *VecTupTy = TargetExtType::get(
LI->getContext(), "riscv.vector.tuple",
@@ -22051,10 +22051,10 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(
VectorType *VTy = cast<VectorType>(II->getType());
VectorType *InVTy = cast<VectorType>(II->getOperand(0)->getType());
+ const DataLayout &DL = SI->getDataLayout();
if (!isLegalInterleavedAccessType(InVTy, Factor, SI->getAlign(),
- SI->getPointerAddressSpace(),
- SI->getDataLayout()))
+ SI->getPointerAddressSpace(), DL))
return false;
Function *VssegNFunc;
@@ -22075,7 +22075,7 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(
Intrinsic::riscv_vsseg6, Intrinsic::riscv_vsseg7,
Intrinsic::riscv_vsseg8};
- unsigned SEW = InVTy->getElementType()->getScalarSizeInBits();
+ unsigned SEW = DL.getTypeSizeInBits(InVTy->getElementType());
unsigned NumElts = InVTy->getElementCount().getKnownMinValue();
Type *VecTupTy = TargetExtType::get(
SI->getContext(), "riscv.vector.tuple",
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
index e2f956ca03ff8e..54373d94f8f5f3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m | FileCheck %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+m | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV32 %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV64 %s
; Integers
@@ -263,9 +263,27 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_load_
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
}
+define {<vscale x 2 x ptr>, <vscale x 2 x ptr>} @vector_deinterleave_load_nxv2p0_nxv4p0(ptr %p) {
+; RV32-LABEL: vector_deinterleave_load_nxv2p0_nxv4p0:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; RV32-NEXT: vlseg2e32.v v8, (a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vector_deinterleave_load_nxv2p0_nxv4p0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vlseg2e64.v v8, (a0)
+; RV64-NEXT: ret
+ %vec = load <vscale x 4 x ptr>, ptr %p
+ %retval = call {<vscale x 2 x ptr>, <vscale x 2 x ptr>} @llvm.vector.deinterleave2.nxv4p0(<vscale x 4 x ptr> %vec)
+ ret {<vscale x 2 x ptr>, <vscale x 2 x ptr>} %retval
+}
+
declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half>)
declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half>)
declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float>)
declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half>)
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
+declare {<vscale x 2 x ptr>, <vscale x 2 x ptr>} @llvm.vector.deinterleave2.nxv4p0(<vscale x 4 x ptr>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index 5ebf63f0a4411e..a06aa2d02b11b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck --check-prefixes=CHECK,RV32 %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck --check-prefixes=CHECK,RV64 %s
; Integers
@@ -218,6 +218,22 @@ define void @vector_interleave_store_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <
ret void
}
+define void @vector_interleave_store_nxv4p0_nxv2p0(<vscale x 2 x ptr> %a, <vscale x 2 x ptr> %b, ptr %p) {
+; RV32-LABEL: vector_interleave_store_nxv4p0_nxv2p0:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; RV32-NEXT: vsseg2e32.v v8, (a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vector_interleave_store_nxv4p0_nxv2p0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vsseg2e64.v v8, (a0)
+; RV64-NEXT: ret
+ %res = call <vscale x 4 x ptr> @llvm.vector.interleave2.nxv4p0(<vscale x 2 x ptr> %a, <vscale x 2 x ptr> %b)
+ store <vscale x 4 x ptr> %res, ptr %p
+ ret void
+}
declare <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half>, <vscale x 2 x half>)
declare <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half>, <vscale x 4 x half>)
@@ -225,3 +241,4 @@ declare <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x floa
declare <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half>, <vscale x 8 x half>)
declare <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)
declare <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double>, <vscale x 2 x double>)
+declare <vscale x 4 x ptr> @llvm.vector.interleave2.nxv4p0(<vscale x 2 x ptr>, <vscale x 2 x ptr>)
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