[llvm] [RISCV] Fold PseudoVMV_V_V with undef passthru, handling policy (PR #106943)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 19:24:25 PDT 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/106943
>From 1620005f7e80affc09676dfcb7d4fcc9160650c6 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 4 Sep 2024 13:44:59 +0800
Subject: [PATCH 1/2] [RISCV] Fold PseudoVMV_V_V with undef passthru, handling
policy
If a vmv.v.v has an undef passthru then we can just replace it with its input operand, since the tail is completely undefined.
This is a reattempt of #106840, but also checks to see if the input was a pseudo where we can relax its tail policy to undef.
This also means we don't need to check for undef passthrus in foldVMV_V_V anymore because they will be handled by foldUndefPassthruVMV_V_V.
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 39 +++++++++++++++++--
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir | 1 -
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.ll | 4 +-
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 3 +-
4 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 35c3bc9708d91a..3e6938b3ec8242 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -66,6 +66,7 @@ class RISCVVectorPeephole : public MachineFunctionPass {
bool convertToWholeRegister(MachineInstr &MI) const;
bool convertToUnmasked(MachineInstr &MI) const;
bool convertVMergeToVMv(MachineInstr &MI) const;
+ bool foldUndefPassthruVMV_V_V(MachineInstr &MI);
bool foldVMV_V_V(MachineInstr &MI);
bool isAllOnesMask(const MachineInstr *MaskDef) const;
@@ -472,6 +473,38 @@ bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
return true;
}
+/// If a PseudoVMV_V_V's passthru is undef then we can replace it with its input
+bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
+ if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMV_V_V)
+ return false;
+ if (MI.getOperand(1).getReg() != RISCV::NoRegister)
+ return false;
+
+ // If the input was a pseudo with a policy operand, we can give it a tail
+ // agnostic policy if MI's undef tail subsumes the input's.
+ MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
+ if (Src && !Src->hasUnmodeledSideEffects() &&
+ MRI->hasOneUse(MI.getOperand(2).getReg()) &&
+ RISCVII::hasVLOp(Src->getDesc().TSFlags) &&
+ RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags) &&
+ getSEWLMULRatio(MI) == getSEWLMULRatio(*Src)) {
+ const MachineOperand &MIVL = MI.getOperand(3);
+ const MachineOperand &SrcVL =
+ Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
+
+ MachineOperand &SrcPolicy =
+ Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc()));
+
+ if (isVLKnownLE(MIVL, SrcVL))
+ SrcPolicy.setImm(SrcPolicy.getImm() | RISCVII::TAIL_AGNOSTIC);
+ }
+
+ MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
+ MI.eraseFromParent();
+ V0Defs.erase(&MI);
+ return true;
+}
+
/// If a PseudoVMV_V_V is the only user of its input, fold its passthru and VL
/// into it.
///
@@ -531,9 +564,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
// If MI was tail agnostic and the VL didn't increase, preserve it.
int64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
- bool TailAgnostic = (MI.getOperand(5).getImm() & RISCVII::TAIL_AGNOSTIC) ||
- Passthru.getReg() == RISCV::NoRegister;
- if (TailAgnostic && isVLKnownLE(MI.getOperand(3), SrcVL))
+ if ((MI.getOperand(5).getImm() & RISCVII::TAIL_AGNOSTIC) &&
+ isVLKnownLE(MI.getOperand(3), SrcVL))
Policy |= RISCVII::TAIL_AGNOSTIC;
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
@@ -584,6 +616,7 @@ bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
Changed |= convertToUnmasked(MI);
Changed |= convertToWholeRegister(MI);
Changed |= convertVMergeToVMv(MI);
+ Changed |= foldUndefPassthruVMV_V_V(MI);
Changed |= foldVMV_V_V(MI);
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
index 1419eede6ca9d1..19a918148e6eb8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -15,7 +15,6 @@ body: |
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
; CHECK-NEXT: $v0 = COPY %mask
- ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 $noreg, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
%false:vr = COPY $v8
%true:vr = COPY $v9
%avl:gprnox0 = COPY $x1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
index c1602c912da635..7f248a39b54fa9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
@@ -199,10 +199,8 @@ define <vscale x 2 x i32> @unfoldable_mismatched_sew(<vscale x 2 x i32> %passthr
define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl) {
; CHECK-LABEL: undef_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl)
%b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index 7e2ac0e26f251f..6858231bf0e6cb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -69,8 +69,7 @@ body: |
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %passthru:vr = COPY $v8
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 1 /* ta, mu */
%passthru:vr = COPY $v8
%x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
%y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
>From 854d924132de41faba5a4626bddf0fb6747d746e Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 5 Sep 2024 10:11:11 +0800
Subject: [PATCH 2/2] Address comments, also don't attempt further folds if MI
was deleted
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 3e6938b3ec8242..026e0a365b8dcb 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -499,7 +499,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
SrcPolicy.setImm(SrcPolicy.getImm() | RISCVII::TAIL_AGNOSTIC);
}
- MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
+ MRI->replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
MI.eraseFromParent();
V0Defs.erase(&MI);
return true;
@@ -616,7 +616,10 @@ bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
Changed |= convertToUnmasked(MI);
Changed |= convertToWholeRegister(MI);
Changed |= convertVMergeToVMv(MI);
- Changed |= foldUndefPassthruVMV_V_V(MI);
+ if (foldUndefPassthruVMV_V_V(MI)) {
+ Changed |= true;
+ continue; // MI is erased
+ }
Changed |= foldVMV_V_V(MI);
}
}
More information about the llvm-commits
mailing list