[llvm] ef1ef03 - [BPF] Fix dst/val mismatch in class ATOMIC_NOFETCH (#107288)

[via llvm-commits]

Author: yonghong-song
Date: 2024-09-04T17:38:25-07:00
New Revision: ef1ef03d4c1014d41713feb0c7edc4d0e36982f4

URL: https://github.com/llvm/llvm-project/commit/ef1ef03d4c1014d41713feb0c7edc4d0e36982f4
DIFF: https://github.com/llvm/llvm-project/commit/ef1ef03d4c1014d41713feb0c7edc4d0e36982f4.diff

LOG: [BPF] Fix dst/val mismatch in class ATOMIC_NOFETCH (#107288)

All ATOMIC_NOFETCH insns have "$dst = $val" constraints. So let us
enforce "$dst = $val" having the same register type in ATOMIC_NOFETCH as
well.

Currently, things work since ATOMIC_NOFETCH does not have source code
pattern matching. I am experimenting to introduce memory ordering to
BPFInstrInfo.td file and pattern matching will be needed. Eventually,
for atomic_fetch_*() insns locked insns could be generated if memory
ordering is memory_order_relaxed.

[1] https://lore.kernel.org/bpf/7b941f53-2a05-48ec-9032-8f106face3a3@linux.dev/

Added: 
    

Modified: 
    llvm/lib/Target/BPF/BPFInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
index 6c750af5c2fd92..f7e17901c7ed5e 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -790,7 +790,7 @@ let Predicates = [BPFNoALU32] in {
 class ATOMIC_NOFETCH<BPFWidthModifer SizeOp, string OpType, RegisterClass RegTp,
                      BPFArithOp Opc, string Opstr>
     : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value,
-                 (outs GPR:$dst),
+                 (outs RegTp:$dst),
                  (ins MEMri:$addr, RegTp:$val),
                  "lock *(" #OpType# " *)($addr) " #Opstr# "= $val",
                  []> {